Compaq EV67, 21264 11describes the Ibox control register fields, 16Internal Processor Registers

Ibox IPRs

Figure 5–22 Ibox Control Register

63 48 47 30 29 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 3 2 1 0

SEXT(VPTB[47])

VPTB[47:30]

CHIP_ID[5:0]

BIST_FAIL

TB_MB_EN

MCHK_EN

ST_WAIT_64K

PCT1_EN

PCT0_EN

SINGLE_ISSUE_H

VA_FORM_32

VA_48

SL_RCV

SL_XMIT

HWE

BP_MODE[1:0]

SBE[1:0]

SDE[1:0]

SPE[2:0]

IC_EN[1:0]

SPCE

LK99-0029A

Table 5–11describes the Ibox control register fields.

Table 5–11 Ibox Control Register Fields Description

Name	Extent	Type	Description
SEXT(VPTB[47])	[63:48]	RW,0	Sign extended VPTB[47].
VPTB[47:30]	[47:30]	RW,0	Virtual Page Table Base. See Section 5.1.5 for details.
CHIP_ID[5:0]	[29:24]	RO	This is a read-only field that supplies the revision ID number
			for the 21264/EV67 part.
			21264/EV67 pass 2.2.2 ID is 0011102.
			21264/EV67 pass 2.2.3 ID is 0011112.
			21264/EV67 pass 2.4	ID is 0011002.
			21264/EV67 pass 2.5	ID is 0001112.
BIST_FAIL	[23]	RO,0	Indicates the status of BiST (clear = pass, set = fail),
			described in Section 11.5.1.
TB_MB_EN	[22]	RW,0	When set, the hardware ensures that the virtual-mode loads
			in DTB and ITB fill flows that access the page table and the

subsequent virtual mode load or store that is being retried are ‘ordered’ relative to another processor’s stores. This must be set for multiprocessor systems in which no MB instruction is present in the TB fill flow, unless there are other mecha- nisms present that ensure coherency.

5–16Internal Processor Registers Alpha 21264/EV67 Hardware Reference Manual