Compaq EV67 Data Error Correction Code, Icache Data or Tag Parity Error, Dcache Tag Parity Error

Data Error Correction Code

8.1 Data Error Correction Code

The 21264/EV67 supports a quadword error correction code (ECC) for the system data bus. ECC is generated by the 21264/EV67 for all memory write transactions (WrVictimBlk) emitted from the 21264/EV67 and for all probe data. ECC is also checked on every memory read transaction for single-bit correction and double-bit error detection. Bcache data is checked for fills to the Dcache and Icache, and for Bcache-to- system transfers that are initiated by a probe (if enabled by the CSR ENABLE_PROBE_CHECK).

The 21264/EV67 ECC implementation corrects single-bit errors in hardware.

I/O write transaction data will not have a valid ECC (the ECC bits must be ignored by the system). Also, ECC checking is not performed on I/O read data.

Error detection and correction can be enabled/disabled by way of Mbox IPR

DC_CTL[DCDAT_ERR_EN].

Table 8–2shows the ECC code.

Table 8–2 64-Bit Data and Check Bit ECC Code

11 1111 1111 2222 2222 2233 3333 3333 4444 4444 4455 5555 5555 6666 CCCC CCCC 0123 4567 8901 2345 6789 0123 4567 8901 2345 6789 0123 4567 8901 2345 6789 0123 0123 4567

CB0 0111 0100 1101 0010 0111 0100 1101 0010 1000 1011 0010 1101 1000 1011 0010 1101 1000 0000 CB1 1110 1010 1010 1000 1110 1010 1010 1000 1110 1010 1010 1000 1110 1010 1010 1000 0100 0000 CB2 1001 1001 0110 0101 1001 1001 0110 0101 1001 1001 0110 0101 1001 1001 0110 0101 0010 0000 CB3 1100 0111 0001 1100 1100 0111 0001 1100 1100 0111 0001 1100 1100 0111 0001 1100 0001 0000 CB4 0011 1111 0000 0011 0011 1111 0000 0011 0011 1111 0000 0011 0011 1111 0000 0011 0000 1000 CB5 0000 0000 1111 1111 0000 0000 1111 1111 0000 0000 1111 1111 0000 0000 1111 1111 0000 0100 CB6 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 0000 0010 CB7 1111 1111 0000 0000 0000 0000 1111 1111 0000 0000 1111 1111 1111 1111 0000 0000 0000 0001

8.2 Icache Data or Tag Parity Error

The following actions are performed when an Icache data or tag parity error occurs.

1.When the hardware detects an error during an Icache read transaction, it traps and replays the instructions that were fetched during the error, then flushes the entire Icache so the re-fetched instructions do not come directly from the Icache.

2.I_STAT[PAR] is set.

3.A corrected read data (CRD) interrupt is posted, when enabled. (Pass 3 only)

8.3Dcache Tag Parity Error

The primary copies of the Dcache tags are used only when servicing 21264/EV67-gener- ated load and store instructions.There are correctable and uncorrectable forms of this error. If an issued load or store instruction detects a Dcache tag parity error, the following actions are performed:

1.MM_STAT[DC_TAG_PERR] is set.

2.A Dstream fault (DFAULT) is taken.

8–2 Error Detection and Error Handling Alpha 21264/EV67 Hardware Reference Manual