Compaq 21264, EV67 specifications Restriction 22 HWRET/STALL After Hwmtpr IS0/IS1

Restriction 22: HW_RET/STALL After HW_MTPR IS0/IS1

BIS R31, R31, R31

HW_MTPR R9, ASN0, SCBD<4>

HW_MTPR R9, ASN1, SCBD<7>

This sequence guarantees, through the register dependency on R0, that neither

HW_MTPR are issued before scoreboard bits [7:4] are cleared. In addition, there must be a HW_RET/STALL after a HW_MTPR ASN0/HW_MTPR ASN1 pair. Finally, these two writes must be executed atomically, that is, either both must be retired or nei- ther may be retired.

D.18 Restriction 22: HW_RET/STALL After HW_MTPR IS0/IS1

There must be a scoreboard bit-to-register dependency chain to prevent either

HW_MTPR IS0 or HW_MTPR IS1 from issuing instructions while any of scoreboard bits [7:4] are set. The following example contains a code sequence that creates the dependency chain.

HW_MFPR R0, VA, SCBD<7,6,5,4>,R0

XOR R0, R0, R0

BIS R0, R9, R9

BIS R31 ,R31, R31

HW_MTPR R9, IS0, SCBD<6>

HW_MTPR R9, IS1, SCBD<7>

This sequence guarantees, through the register dependency on R0, that neither HW_MTPR are issued before scoreboard bits [7:4] are cleared. There must be a HW_RET/STALL after an HW_MTPR IS0/HW_MTPR IS1 pair. Also, these two writes must be executed atomically, that is, either both must be retired or neither may be retired.

D.19 Restriction 23: HW_ST/P/CONDITIONAL Does Not Clear the Lock Flag

AHW_ST/P/CONDITIONAL will not clear the lock flag such that a successive store- conditional (either STx_C or HW_ST/C) might succeed even in the absence of a load- locked instruction. In the 21264/EV67, a store-conditional is forced to fail if there is an intervening memory operation between the store-conditional and its address-matching LDxL. The following example shows the memory operations.

LDL/Q/F/G/S/T

STL/Q/F/G/S/T

LDQ_U (not to R31)

STQ_U

Absent from this list are HW_LD (any type), HW_ST (any type), ECB, and WH64. Their absence implies that they will not force a subsequent store-conditional instruction to fail. PALcode must insert a memory operation from the above list after a HW_ST/ CONDITIONAL in order to force a future store-conditional to fail if it was not pre- ceded by a load-locked operation:

HW_LDxL

Alpha 21264/EV67 Hardware Reference Manual PALcode Restrictions and Guidelines D–13