Compaq EV67, 21264 specifications 36Internal Processor Registers

Cbox CSRs and IPRs

Table 5–24 Cbox WRITE_ONCE Chain Order (Continued)

Cbox WRITE_ONCE Chain	Description
BC_TAG_DDM_RISE_EN[0]	Enables the update of the 21264/EV67 Bcache tag outputs based on
	the rising edge of the forwarded clock.
BC_CLKFWD_ENABLE[0]	Enable clock forwarding on the Bcache interface.
BC_RCV_MUX_CNT_PRESET[0:1]	Initial value for the Bcache clock forwarding unload pointer FIFO.
BC_LATE_WRITE_UPPER[0]	Duplicate CSR.
SYS_DDM_FALL_EN[0]	Enables the update of the 21264/EV67 system outputs based on the
	falling edge of the system forwarded clock.
SYS_DDM_RISE_EN[0]	Enables the update of the 21264/EV67 system outputs based on the
	rising edge of the system forwarded clock.
SYS_CLKFWD_ENABLE[0]	Enables clock forwarding on the system interface.
SYS_RCV_MUX_CNT_PRESET[0:1]	Initial value for the system clock forwarding unload pointer FIFO.
SYS_CLK_DELAY[0:1]	Delay of 0 to 2 phases between the forwarded clock out and
	address/data.
SYS_DDMR_ENABLE[0]	Enables the rising edge of the system forwarded clock (always
	enabled).
SYS_DDMF_ENABLE[0]	Enables the falling edge of the system forwarded clock (always
	enabled).
BC_DDM_FALL_EN[0]	Enables update of data/address on the rising edge of the system for-
	warded clock.
BC_DDM_RISE_EN[0]	Enables the update of data/address on the falling edge of the system
	forwarded clock.
BC_CLKFWD_ENABLE	Duplicate CSR.
BC_RCV_MUX_CNT_PRESET[0:1]	Duplicate CSR.
BC_CLK_DELAY[0:1]	Duplicate CSR.
BC_DDMR_ENABLE	Duplicate CSR.
BC_DDMF_ENABLE	Duplicate CSR.
SYS_DDM_FALL_EN	Duplicate CSR.
SYS_DDM_RISE_EN	Duplicate CSR.
SYS_CLKFWD_ENABLE	Duplicate CSR.
SYS_RCV_MUX_CNT_PRESET[0:1]	Duplicate CSR.
SYS_CLK_DELAY[0:1]	Duplicate CSR.
SYS_DDMR_ENABLE	Duplicate CSR.
SYS_DDMF_ENABLE	Duplicate CSR.
BC_DDM_FALL_EN	Duplicate CSR.
BC_DDM_RISE_EN	Duplicate CSR.
BC_CLKFWD_ENABLE	Duplicate CSR.
BC_RCV_MUX_CNT_PRESET[0:1]	Duplicate CSR.

5–36Internal Processor Registers Alpha 21264/EV67 Hardware Reference Manual