Energy Star Certification and Sleep Mode Flow | Compaq 21264, EV67

Energy Star Certification and Sleep Mode Flow

Figure 7–2 Fault Reset Sequence of Operation

state

SromOE_L

ClkFwdRst_H

internal ClkFwdRst

internal clks aligned

e

RUN	WAIT_FAULT_RESET		WAIT_ClkFwdRst0	WAIT_ClkFwdRst1	RUN
	a	b	c	g
			no min	no min

A f

external Clks

FM-06488B.AI4

7.3 Energy Star Certification and Sleep Mode Flow

The 21264/EV67 is Energy Star compliant. Energy Star is a program administered by the Environmental Protection Agency to reduce energy consumption. For compliance, a computer must automatically enter a low power sleep mode using 30 watts or less after a specified period of inactivity. When the system is awakened, the user shall be returned automatically to the same situation that existed prior to entering sleep mode.

During normal operation, the 21264/EV67 encounters inactive periods and enters a mode that saves the entire active processor state to memory.

The PALcode is responsible for saving all necessary state to DRAM and flushing the caches.

The sleep mode sequence of operations is triggered by the PALcode twice performing a HW_MTPR to the Ibox SLEEP IPR. The first write prevents the assertion of ClkFwdRst_H from fault-resetting the chip.

The PALcode then informs the system, in an implementation-dependent way, that it may assert ClkFwdRst_H.

On the second HW_MTPR to the SLEEP IPR, the PLL begins to ramp down and the 21264/EV67 can then respond to the ClkFwdRst_H that was asserted by the system, causing the outgoing clocks from the 21264/EV67 to stop.

The PLL ramp-down sequence takes exactly the same amount of time as the ramp up sequence described in Section 7.1.3. The same internal duration counter is used and the reset state machine transitions through the DOWN1, DOWN2, and DOWN3 states which have similar PLL divisor ratios and clock speeds to the RAMP2, RAMP1, and WAIT_NOMINAL states.

Alpha 21264/EV67 Hardware Reference Manual

Initialization and Configuration 7–9

Image 217

Compaq 21264, EV67 specifications Energy Star Certification and Sleep Mode Flow

Contents

Alpha 21264A Microprocessor Revision/Update InformationHardware Reference Manual DS-0028A-TE Alpha 21264/EV67 Hardware Reference Manual Table of Contents Cache and External Interfaces Hardware Interface Internal Processor Registers Privileged Architecture Library Code Mffpcr Mtfpcr Initialization and Configuration Testability and Diagnostics Error Detection and Error HandlingElectrical Data Thermal Management 21264/EV67 Boundary-Scan Register Alpha Instruction Set Glossary Index 21264/EV67-to-Bcache Pin Interconnections Figures Xii Tables Xiv VDD Idcpower Page Preface ContentAudience Documentation Included by Reference For example Terminology and ConventionsAbbreviations W1S W1CAddresses Aligned and Unaligned Data Units Signal NamesDo Not Care External Undefined Do not care. a capital X represents any valid value Page Architecture IntroductionIntroduction Addressing ArchitectureInteger Data Types Floating-Point Data Types 21264/EV67 Microprocessor Features 21264/EV67 Microprocessor Features 21264/EV67 Microprocessor Features 21264/EV67 Microarchitecture Internal ArchitectureInternal Architecture 21264/EV67 Microarchitecture Instruction Fetch, Issue, and Retire UnitVirtual Program Counter Logic Branch Predictor 21264/EV67 Block Diagram Global Predictor Local Predictor Instruction-Stream Translation Buffer Choice Predictor Instruction Fetch Logic Integer Issue QueueRegister Rename Maps Hwret Floating-Point Issue Queue Exception and Interrupt Logic Integer Execution UnitRetire Logic Integer Execution Unit-Clusters 0 PERR, MINxxx, MAXxxx, UNPKxx, PKxx 10Internal Architecture Floating-Point Execution Unit Onchip Caches External Cache and System Interface Unit21264/EV67 contains two onchip primary-level caches Data Cache Memory Reference Unit12Internal Architecture Pipeline Organization Pipeline OrganizationSrom Interface Miss address file MAF Dstream translation buffer DTB Stage 1 Instruction Slot Stage 0 Instruction Fetch14Internal Architecture Stage 2 Map Stage 3 Issue Instruction Issue Rules Instruction Issue RulesPipeline Aborts Ebox and Fbox pipelines begin execution Instruction Name, Pipeline, and Types Instruction Issue Rules Instruction Group Definitions FTOIS, Ftoit Ebox SlottingITOFS, ITOFF, Itoft Instruction Group Definitions and Pipeline Unit U U L E L U E E L L E U Instruction Class Latency in Cycles Instruction Issue Rules Instruction LatenciesHwmfpr 20Internal Architecture Instruction Retire Rules Instruction Retire RulesMinimum Retire Latencies for Instruction Classes Retire of Operate Instructions into R31/F31 Retire of Operate Instructions into R31/F31Floating-Point Divide/Square Root Early Retire BSR/JSR Load Instructions to R31 and F31 Load Instructions to R31 and F31Prefetch with Modify Intent LDS Instruction Instructions Retired Without Execution Prefetch with the LDxL / STxC Instruction Sequence Special Cases of Alpha Instruction ExecutionLoad Hit Speculation 24Internal Architecture Pipeline Timing for Integer Load Instructions Special Cases of Alpha Instruction Execution Cmov Instruction Floating-Point Store Instructions26Internal Architecture Memory and I/O Address Space Instructions Memory and I/O Address Space InstructionsMemory Address Space Load Instructions Rules for I/O Address Space Load Instruction Data Merging 2 I/O Address Space Load Instructions28Internal Architecture 8shows some of the following rules 4 I/O Address Space Store InstructionsRules for I/O Address Space Store Instruction Data Merging Instruction Ordering MAF Memory Address Space Merging RulesMAF Memory Address Space Merging Rules MAF Merging Rules Replay Traps Replay TrapsMbox Order Traps 10 Memory Reference Ordering Write Buffer and the WMB Instruction 12 I/O Write Buffer and the WMB InstructionOther Mbox Replay Traps Memory Barrier MB/WMB/TB Fill Flow MB Instruction Processing TB Fill Flow WMB Instruction Processing12 TB Fill Flow Example Sequence 34Internal Architecture 13 TB Fill Flow Example Sequence Floating-Point Control Register Performance Measurement Support-Performance CountersPerformance Measurement Support-Performance Counters Floating-point control register Fpcr is shown in Figure Floating-Point Control Register Amask and Implver Instruction Values Amask and Implver Instruction ValuesAmask Implver Design Examples Design Examples 40Internal Architecture 13 Typical Multiprocessor Configuration Hardware Interface 21264/EV67 Microprocessor Logic SymbolHardware Interface 21264/EV67 Microprocessor Logic Symbol 21264/EV67 Microprocessor Logic Symbol 21264/EV67 Signal Names and Functions 21264/EV67 Signal Names and FunctionsSignal Pin Types Definitions 21264/EV67 Signal Descriptions Dcokh Pllvdd TestStatH 21264/EV67 Signal Descriptions by Function SysVref Domain SysAddInL140 Pin Assignments Pin List Sorted by Signal NamePin Assignments AC1 Pllvdd 10Hardware Interface AA5 12Hardware Interface Pin List Sorted by PGA Location SysDataL28 14Hardware Interface BcDataH70 SysDataL5 16Hardware Interface Ground and Power VSS and VDD Pin List Mechanical Specifications Mechanical Specifications 21264/EV67 Packaging 21264/EV67 Packaging18Hardware Interface 21264/EV67 Bottom View Pin Up Page Introduction to the External Interfaces Cache and External InterfacesCache and External Interfaces Introduction to the External Interfaces 21264/EV67 System and Bcache Interfaces System Interface Physical Address Considerations Commands and AddressesPhysical Address Considerations Second-Level Cache Bcache Interface MB/WMB ECB I/O Physical Address Considerations Bcache Structure Bcache Interface SignalsBcache Structure System Duplicate Tag Stores Cache Coherency Victim Data BufferVictim Data Buffer Cache Coherency Basics Cache Block States Cache Coherency2lists the cache block states supported by the 21264/EV67 21264/EV67-Supported Cache Block States Cache Block State Transitions System Responses to 21264/EV67 CommandsCache Block State Transitions 10Cache and External Interfaces Cache Coherency Using SysDc Commands 12Cache and External Interfaces Dcache States and Duplicate Tags Lock Mechanism Lock Mechanism14Cache and External Interfaces Liveness and Fairness Internal Eviction of LDxL Blocks System Port System Port16Cache and External Interfaces System Port Pins System Port Pins Programming Values for System Interface Clocks System Port Programming the System Interface ClocksProgram Values for Data-Sample/Drive CSRs 18Cache and External Interfaces Bank Interleave on Cache Block Boundary Mode 3 21264/EV67-to-System CommandsForwarded Clocks and Frame Clock Ratio 11 Page Hit Mode of Operation Hit Mode12 21264/EV67-to-System Command Fields Definitions 12describes the field definitions for Tables 4-10and 14describes the 21264/EV67-to-system commands 4 21264/EV67-to-System Commands Descriptions14 21264/EV67-to-System Commands Descriptions 13 Maximum Physical Address for Short Bus Format 22Cache and External Interfaces 15 Programming INVALTODIRTYENABLE10 16 Programming SETDIRTYENABLE20 ProbeResponse Commands Command40 =17 21264/EV67 ProbeResponse Command 24Cache and External Interfaces 18describes the ProbeResponse command fields SysAck and 21264/EV67-to-System Commands Flow Control18 ProbeResponse Fields Descriptions Probe Commands Four Cycles System-to-21264/EV67 Commands19 System-to-21264/EV67 Probe Commands RVB RPB 21 lists the data movement selected by Probe43 20 System-to-21264/EV67 Probe Commands Fields Descriptions22lists the next cache block state selected by Probe20 21 Data Movement Selection by Probe43 23 Data Transfer Command Format Data Transfer Commands Two Cycles28Cache and External Interfaces 24 SysDc40 Field Description 24describes the SysDc40 field 8.1 21264/EV67 Clock Basics Data Movement In and Out of the 21264/EV6730Cache and External Interfaces Fast Data Mode 32Cache and External Interfaces 25 Sysclk Cycles Between SysAddOut and SysData 26 Cbox CSR SYSDCDELAY40 Examples 26shows four example configurations and shows their useFast Data Disable Mode SysDataInValidL and SysDataOutValidL 27 Four Timing ExamplesSysDataInValidL 34Cache and External Interfaces SysFillValidL SysDataOutValidL 28 Data Wrapping Rules Data Wrapping36Cache and External Interfaces 29 System Wrap and Deliver Data 30defines the interleaved scheme for the wrap order30 Wrap Interleave Order 31defines the wrap order for double-pumped data transfers Nonexistent Memory Processing31 Wrap Order for Double-Pumped Data Transfers 38Cache and External Interfaces 21264/EV67 Command NXM Address System/21264/EV67 Response Ordering of System Port Transactions 10.1 21264/EV67 Commands and System Probes40Cache and External Interfaces System Port Bcache Port Bcache Port 36 Bcache Port Pins Bcache Port Pins35 Range of Maximum Bcache Clock Ratios 44Cache and External Interfaces Bcache Clocking 38 BCCLKDELAY10 Values 37 BCCPUCLKDELAY10 ValuesSetting the Period of the Cache Clock 46Cache and External Interfaces 39 Program Values to Set the Cache Clock Period Single-Data 41 Data-Sample/Drive Cbox CSRs Bcache TransactionsBcache Data Read and Tag Read Transactions 48Cache and External Interfaces Bcache Data Write Transactions When the ratio is odd, bcfrm is twice the ratio When the ratio is even, bcfrm is equal to the ratioFor example, in single-data mode Dual-data mode, bcfrm is twice the ratio 50Cache and External Interfaces Relationship Between Write-to-Read Bcwrrdbubbles and wrrd Pin DescriptionsRelationship Between Read-to-Write Bcrdwrbubbles and rdwr BcAddH234 44lists the combination of control pin assertion for 47 Control Pin Assertion for Ramtype D 46 Control Pin Assertion for Ramtype CBcDataInClkH and BcTagInClkH Interrupts Bcache Banking InterruptsDisabling the Bcache for Debugging 54Cache and External Interfaces Internal Processor Registers Internal Processor Registers Mbox IPRs Ebox IPRs Ebox IPRsCycle Counter Register CC Cycle Counter Control Register Ccctl Virtual Address Control Register Vactl Virtual Address Register VA2describes the Ccctl register fields Cycle Counter Control Register Fields Description 3describes the virtual address control register fields Virtual Address Format Register VaformVirtual Address Control Register Fields Description VAFORM32 Ibox IPRs Ibox IPRsITB Tag Array Write Register Itbtag ITB PTE Array Write Register Itbpte ITB Invalidate All Register Itbia ITB Invalidate All Process ASM=0 Register ItbiapITB Invalidate Single Register Itbis Exception Address Register Excaddr Ibox IPRs ProfileMe PC Register Pmpc4describes the ProfileMe PC register fields ProfileMe PC Fields Description 13shows Ivaform when ICTLVA48 equals 0 ICTLVAFORM32 equals Interrupt Enable and Current Processor Mode Register Iercm Iercm Register Fields Description Software Interrupt Request Register Sirr10Internal Processor Registers 6describes the software interrupt request register fields Interrupt Summary Register IsumSoftware Interrupt Request Register Fields Description 7describes the interrupt summary register fields Hardware Interrupt Clear Register HwintclrInterrupt Summary Register Fields Description 12Internal Processor Registers 8describes the hardware interrupt clear register fields Exception Summary Register ExcsumHardware Interrupt Clear Register Fields Description Mchkd W1C Exception Summary Register Fields Description 9describes the exception summary register fields14Internal Processor Registers Ibox Control Register Ictl PAL Base Register Palbase10describes the PAL base register fields 10 PAL Base Register Fields Description 11 Ibox Control Register Fields Description 11describes the Ibox control register fields16Internal Processor Registers Mchken SingleissuehSTWAIT64K PCT1EN Spce Ibox Status Register Istat18Internal Processor Registers 12 Ibox Status Register Fields Description 12describes the Ibox status register fieldsMIS TRP 20Internal Processor Registers Ibox IPRs Icache Flush Register Icflush Sleep Mode Register SleepIcache Flush ASM Register Icflushasm Clear Virtual-to-Physical Map Register Clrmap 14 Process Context Register Fields Description 14describes the process context register fields22Internal Processor Registers FPE Performance Counter Control Register PctrctlPpce 15 Performance Counter Control Register Fields Description 15describes the performance counter control register fields24Internal Processor Registers Mbox IPRs Mbox IPRsDTB Tag Array Write Registers 0 and 1 DTBTAG0, DTBTAG1 16 Performance Counter Control Register Input Select Fields 26Internal Processor Registers DTB Alternate Processor Mode Register Dtbaltmode Dstream TB Invalidate All Process ASM=0 Register Dtbiap 17 DTB Alternate Processor Mode Register Fields DescriptionDstream TB Invalidate All Register Dtbia Dstream TB Invalidate Single Registers 0 and 1 DTBIS0,1 18describes the memory management status register fields Memory Management Status Register Mmstat18 Memory Management Status Register Fields Description 28Internal Processor Registers For Mbox Control Register MctlACV Dcache Control Register Dcctl Erences to superpages result in access violations19describes the Mbox control register fields 19 Mbox Control Register Fields Description 20describes the Dcache control register fields Dcache Status Register Dcstat20 Dcache Control Register Fields Description Cbox CSRs and IPRs Cbox CSRs and IPRs21describes the Dcache status register fields 21 Dcache Status Register Fields Description Cbox Shift Register Cshft Cbox CSRs and IPRs Cbox Data Register CdataCbox Writeonce Chain Description 22 describes the Cbox data register fields 34Internal Processor Registers 24 Cbox Writeonce Chain Order Skewedfillmode Mboxbcprbstall BCLATDATAPATTERN031 BCLATTAGPATTERN023 36Internal Processor Registers SYSCLKDELAY10 38Internal Processor Registers Cbox Writemany Chain Description 25 Cbox Writemany Chain Order 25describes the Cbox Writemany chain order from LSB to MSB 40Internal Processor Registers Setdirtyenable = Bcbankenable = 26 Cbox Read IPR Fields Description Cbox CSRs and IPRs Cbox Read Register IPR DescriptionPage PALcode Description Privileged Architecture Library CodePrivileged Architecture Library Code PALmode Environment PALmode Environment Opcodes Reserved for PALcode Required PALcode Function CodesRequired PALcode Function Codes Hwld Instruction Hwst Instruction Opcodes Reserved for PALcode3describes the Hwld instruction fields Hwld Instruction Fields Descriptions 4describes the Hwst instruction fields Hwret InstructionHwst Instruction Fields Descriptions 5describes the Hwret instruction fields Hwmfpr and Hwmtpr InstructionsHwret Instruction Fields Descriptions Hint Internal Processor Register Access Mechanisms Internal Processor Register Access Mechanisms6describes the Hwmfpr and Hwmtpr instructions fields Hwmfpr and Hwmtpr Instructions Fields Descriptions Hardware Structure of Explicitly Written IPRs Paired Instruction Fetch Order IPR Access Ordering 10Privileged Architecture Library Code PALcode Emulation of the Fpcr PALshadow Registers PALcode Entry Points PALcode Exception Entry Locations PALcode Exception Entry Points Translation Buffer TB Fill Flows Translation Buffer TB Fill FlowsDTB Fill 14Privileged Architecture Library Code Tb miss Wr DataWr PTE LD-PTE, write TB 16Privileged Architecture Library Code ITB Fill Performance Counter Support Performance Counter Support Aggregate Mode Programming Guidelines General PrecautionsAggregate Mode Precautions IPRs Used for Performance Counter Support Operation 10 Aggregate Mode Returned IPR ContentsPctrctl SL0 SL1 11shows the counter modes that are used with Aggregate mode ProfileMe Mode Programming GuidelinesThis input counts Mbox replay traps 12 Cmov Decomposed 22Privileged Architecture Library Code 13 ProfileMe Mode Returned IPR Contents Inum retire delay cycles ProfileMe Counting Mode Description Cycle counting Counter Modes for ProfileMe Mode 14shows the counter modes that are used with ProfileMe mode14 ProfileMe Mode Pctrctl Input Select Fields 24Privileged Architecture Library Code Power-Up Reset Flow and the ResetL and Dcokh Pins Initialization and Configuration21264/EV67 Reset State Machine Major Operations Initialization and Configuration Constraints Power-Up Reset Flow and the ResetL and Dcokh Pins Signal Pin Reset State Power Sequencing and Reset State for Signal Pins Pllvdd Clock Forwarding and System Clock Ratio Configuration PLL Pin Signal Names and Initialization State BiST and Srom Load and the TestStatH Pin PLL Ramp Up Power-Up Flow Signals and Their Constraints Clock Forward Reset and System Interface Initialization Fault Reset Flow Fault Reset FlowEffect on IPRs After Fault Reset Energy Star Certification and Sleep Mode Flow Energy Star Certification and Sleep Mode Flow 10Initialization and Configuration Effect on IPRs After Transition Through Sleep Mode Warm Reset Flow Warm Reset FlowSignals and Constraints for the Sleep Mode Sequence Effect on IPRs After Warm Reset 12Initialization and Configuration Initialization Mode ProcessingArray Initialization Array Initialization EVICTENABLE0 Initialization Mode Processing 10 Internal Processor Registers at Power-Up Reset State Internal Processor Register Power-Up Reset State14Initialization and Configuration External Interface Initialization Internal Processor Register Power-Up Reset State Reset State Machine Ieee 1149.1 Test Port ResetIeee 1149.1 Test Port Reset 16Initialization and Configuration 11 21264/EV67 Reset State Machine State Descriptions Reset State Machine 18Initialization and Configuration Phase-Lock Loop PLL Functional Description Phase-Lock Loop PLL Functional DescriptionDifferential Reference Clocks PLL Output Clocks 20Initialization and Configuration Power-Up/Reset Clocking 21264/EV67 Error Detection Mechanisms Error Detection and Error HandlingError Detection and Error Handling Icache Data or Tag Parity Error Data Error Correction CodeDcache Tag Parity Error Data Error Correction Code Dcache Data Single-Bit Correctable ECC Error Dcache Data Single-Bit Correctable ECC ErrorLoad Instruction Dcache Duplicate Tag Parity Error Dcache Store Second ErrorDcache Store Second Error Store Instruction Quadword or Smaller Bcache Data Single-Bit Correctable ECC Error Bcache Tag Parity ErrorBcache Tag Parity Error Icache Fill from Bcache Bcache Victim Read During a Dcache/Bcache Miss Bcache Victim Read Memory/System Port Single-Bit Data Correctable ECC Error Memory/System Port Single-Bit Data Correctable ECC ErrorIcache Fill from Memory Dcache Fill from Memory Bcache Data Single-Bit Correctable ECC Error on a Probe Bcache Data Single-Bit Correctable ECC Error on a Probe Error Case Summary Double-Bit Fill ErrorsDouble-Bit Fill Errors 3summarizes the various error cases and their ramifications 10Error Detection and Error Handling Error Case Summary Mchk Cstatistreammemdbl Mchk CstatdstreambcdblMchk Cstatdstreammemdbl Page Electrical Data Electrical Characteristics1lists the maximum electrical ratings for the 21264/EV67 Maximum Electrical Ratings DC Characteristics DC CharacteristicsSignal Types Idcpower Input DC Reference Pin Idcref VDD IdcpowerInput Differential Amplifier Receiver IDA Input Differential Amplifier Clock Receiver Idaclk Pin Type Open-Drain Output Driver OOD Pin Type Open-Drain Driver for Test Pins OodtpIOZ Codtp 12 Push-Pull Output Clock Driver Oppclk 11 Push-Pull Output Driver OPP AC Characteristics AC CharacteristicsAC Test Conditions TSU TDH 13 AC Specifications TSU1 TDH2 AC Characteristics Page Ambient temperature requirement Operating TemperatureOperating Temperature at Heat Sink Center Tc Thermal Management Θca at Various Airflows for 21264/EV67 Operating Temperature10-2Thermal Management Heat Sink Specifications Heat Sink Specifications 10-4Thermal Management Type 1 Heat Sink Type 2 Heat Sink 10-6Thermal Management Type 3 Heat Sink Thermal Design Considerations Thermal Design ConsiderationsPage Test Pins Testability and DiagnosticsDedicated Test Port Pins Testability and Diagnostics SROM/Serial Diagnostic Terminal Port SROM/Serial Diagnostic Terminal Port11-2Testability and Diagnostics Srom Load Operation Ieee 1149.1 Port Ieee 1149.1 PortIeee 1149.1 Instructions and Opcodes TestStatH Pin 11-4Testability and DiagnosticsTestStatH Pin Power-Up Self-Test and Initialization Power-Up Self-Test and InitializationBuilt-in Self-Test Srom Initialization Serial Instruction Cache Load Operation 11-6Testability and Diagnostics Icache Bit Fields in an Srom Line See Appendix B for a listing of the Boundary-Scan RegisterReferences Page Alpha Instruction Summary Alpha Instruction SetTable A-1 Instruction Format and Opcode Notation Alpha Instruction Set A-1 Alpha Instruction Summary Pcd Trap to PALcode Mbr Branch to subroutineOpr 11.24 Cmove if = zero Opr 11.46 Cmove if ≥ zero 17.010 Convert longword to quadword 15.0AF Convert Gfloating to quadword15.0BC Convert quadword to Ffloating 15.0BE Convert quadword to Gfloating 17.02E Fcmove if ≤ zero 17.02F Fcmove if zero17.02C Fcmove if zero 17.02B Fcmove if ≠ zero Opr 13.60 Multiply quadword with integer overflow enable Opr 13.40 Multiply longword with integer overflow enableOpr 1C.31 Pixel error Mem Load Sfloating Mbr 1A.2 Return from subroutine Opr 1C.36 Pack words to bytes Mfc 18.E000 Read and clearMfc 18.C000 Read process cycle counter 18.F000 Read and set Opr 10.02 Scaled add longword by Reserved Opcodes Reserved OpcodesOpcodes Reserved for Compaq Ieee Floating-Point Instructions Ieee Floating-Point Instructions Independent Floating-Point Instructions VAX Floating-Point InstructionsVAX Floating-Point Instructions Opcode Summary Opcode Summary Mem Res Mem Table A-9explains the symbols used in Table A-8Ieee floating-point instruction opcodes Floating-point operate instruction opcodes Ieee Floating-Point Conformance Ieee Floating-Point Conformance14Alpha Instruction Set Alpha Instruction Set A-15 Table A-11 Exceptional Input and Output Conditions Cmptlt Cmptle Input Cmpteq Cmptun Input16Alpha Instruction Set Alpha Instruction Set A-17 Fbeq Fbne Fblt Fble Fbgt Fbge LDS LDT STS STT Cpys CpysnPage Boundary-Scan Register 21264/EV67 Boundary-Scan Register Pllvdd Boundary-Scan Register 21264/EV67 Boundary-Scan Register B-3 421264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B-5 621264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B-7 821264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B-9 1021264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B-11 1221264/EV67 Boundary-Scan Register Serial Icache Load Predecode Values C-1 Serial Icache Load Predecode ValuesPage PALcode Restrictions and Guidelines D-1 PALcode Restrictions and Guidelines 2PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-3 4PALcode Restrictions and Guidelines Initwritemany PALcode Restrictions and Guidelines D-5 6PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-7 8PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-9 Restriction 7 Replay Trap, Interrupt Code Sequence, and STF Restriction 9 PALmode Istream Address Ranges Restriction 10 Duplicate IPR Mode BitsRestriction 9 PALmode Istream Address Ranges 10PALcode Restrictions and Guidelines Restriction 11 Ibox IPR Update Synchronization Restriction 11 Ibox IPR Update SynchronizationRestriction 13 DTB Fill Flow Collision Restriction 14 Hwret Guideline 16 JSR-BAD VA Guideline 20 Ictlsbe Stream Buffer EnableRestriction 21 HWRET/STALL After Hwmtpr ASN0/ASN1 Guideline 16 JSR-BAD VA Restriction 22 HWRET/STALL After Hwmtpr IS0/IS1 Restriction 22 HWRET/STALL After Hwmtpr IS0/IS1PALcode Restrictions and Guidelines D-13 Guideline 26 Conditional Branches in PALcode Restriction 25 Hwmtpr Itbia After ResetRestriction 24 HWRET/STALL After Hwmtpr ICFLUSH, Icflushasm 14PALcode Restrictions and Guidelines Restriction 30 Hwmtpr and Hwmfpr to the Cbox CSR Guideline 29 JSR, JMP, RET, and Jsrcor in PALcodePALcode Restrictions and Guidelines D-15 16PALcode Restrictions and Guidelines Restriction 30 Hwmtpr and Hwmfpr to the Cbox CSR Restriction 32 Pctrctl Update Restriction 31 ICTLVA48 UpdateRestriction 31 ICTLVA48 Update PALcode Restrictions and Guidelines D-17 Restriction 33 Hwld Physical/Lock Use Guideline 35 Hwintclr UpdateRestriction 36 Updating Ictlsde Restriction 37 Updating VACTLVA48 PALcode Restrictions and Guidelines D-19 Restriction 40 Scrubbing a Single-Bit Error 20PALcode Restrictions and Guidelines Restriction 40 Scrubbing a Single-Bit Error Restriction 43 No Trappable Instructions Along with Restriction 42 Updating VACTL, CCCTL, or CC IPRsPALcode Restrictions and Guidelines D-21 22PALcode Restrictions and Guidelines Restriction 47 Cache Eviction for Single-Bit Cache Errors PALcode Restrictions and Guidelines D-23 Restriction 47 Cache Eviction for Single-Bit Cache Errors 24PALcode Restrictions and Guidelines Forwarding Clock Pin Groupings 21264/EV67-to-Bcache Pin InterconnectionsTable E-1 Bcache Forwarding Clock Pin Groupings Late-Write Non-Bursting SSRAMs Late-Write Non-Bursting SSRAMsData Pin Usage Tag Pin Usage Dual-Data Rate SSRAMs Dual-Data Rate SSRAMsData and Tag Pin Usage Table E-4 Dual-Data Rate Ssram Data Pin Usage Table E-5 Dual-Data Rate Ssram Tag Pin Usage Trstl Glossary BIU BSR Cisc CPI CmosCPU CSR Dram DMADTB DTL FET FepromFEU Fpga IDU Gclk Ipga IowbITB Jfet MBO MAFMBZ Mips Naturally Aligned MSINmos Nvram PGA PALPLA Plcc Prom PqfpRAM RAS ROM RiscRTL SAM Simm SdramSIP Sipp TTL StramUart Unaligned Uvprom UnpredictableVAF VDF Writeblock WAR Numerics Index Index-2 Index-3 Index-4 ECC Index-6 Index-7 Index-8 Index-9 Index-10 Index-11 Index-12