Compaq EV67 Instruction Issue Rules, Pipeline Aborts, Ebox and Fbox pipelines begin execution

Instruction Issue Rules

Stage 4 — Register Read

Instructions issued from the issue queues read their operands from the integer and float- ing-point register files and receive bypass data.

Stage 5 — Execute

The Ebox and Fbox pipelines begin execution.

Stage 6 — Dcache Access

Memory reference instructions access the Dcache and data translation buffers. Nor- mally load instructions access the tag and data arrays while store instructions only access the tag arrays. Store data is written to the store queue where it is held until the store instruction is retired. Most integer operate instructions write their register results in this cycle.

2.2.1 Pipeline Aborts

The abort penalty as given is measured from the cycle after the fetch stage of the instruction which triggers the abort to the fetch stage of the new target, ignoring any Ibox pipeline stalls or queuing delay that the triggering instruction might experience. Table 2–1lists the timing associated with each common source of pipeline abort.

Table 2–1 Pipeline Abort Delay (GCLK Cycles)

	Penalty
Abort Condition	(Cycles)	Comments
Branch misprediction	7	Integer or floating-point conditional branch
		misprediction.
JSR misprediction	8	Memory format JSR or HW_RET.
Mbox order trap	14	Load-load order or store-load order.
Other Mbox replay traps	13	—
DTB miss	13	—
ITB miss	7	—
Integer arithmetic trap	12	—
Floating-point arithmetic	13+latency	Add latency of instruction. See Section 2.3.3 for
trap		instruction latencies.

2.3 Instruction Issue Rules

This section defines instruction classes, the functional unit pipelines to which they are issued, and their associated latencies.

2–16Internal Architecture Alpha 21264/EV67 Hardware Reference Manual