5–34

Dcache Status Register

5–32

5–35

Cbox Data Register

5–33

5–36

Cbox Shift Register

5–33

5–37

WRITE_MANY Chain Write Transaction Example

5–39

6–1

HW_LD Instruction Format

6–4

6–2

HW_ST Instruction Format

6–4

6–3

HW_RET Instruction Format

6–6

6–4

HW_MFPR and HW_MTPR Instructions Format

6–6

6–5

Single-Miss DTB Instructions Flow Example

6–14

6–6

ITB Miss Instructions Flow Example

6–16

7–1

Power-Up Timing Sequence

7–3

7–2

Fault Reset Sequence of Operation

7–9

7–3

Sleep Mode Sequence of Operation

7–11

7–4

Example for Initializing Bcache

7–13

7–5

21264/EV67 Reset State Machine State Diagram

7–17

10–1

Type 1 Heat Sink

10–4

10–2

Type 2 Heat Sink

10–5

10–3

Type 3 Heat Sink

10–6

11–1

TAP Controller State Machine

11–4

11–2

TestStat_H Pin Timing During Power-UpBuilt-InSelf-Test (BiST)

11–5

11–3

TestStat_H Pin Timing During Built-InSelf-Initialization (BiSI)

11–5

11–4

SROM Content Map

11–6

xii

Alpha 21264/EV67 Hardware Reference Manual

Page 12
Image 12
Compaq EV67, 21264 specifications Xii