Sysclk Cycles Between SysAddOut and SysData | Compaq EV67, 21264

System Port

The command precedes data by at least one SYSCLK period. Table 4–25shows the number of SYSCLK cycles between SysAddOut and SysData for all system clock ratios (clock forwarded bit times) and system framing clock multiples.

Table 4–25 SYSCLK Cycles Between SysAddOut and SysData

		GCLK/INT_FWD_CLK (Data Rate Ratio)

System framing clock ratio	1.5X	2.0X	2.5X	3.0X	3.5X	4.0X	5.0X	6.0X	7.0X	8.0X
1	4	3	2	2	2	2	1	1	1	1
2	2	2	1	1	1	1	1	1	1	1
4	1	1	1	1	1	1	1	1	1	1

Figure 4–5show a simple example of a fast transfer. The data rate ratio is 1.5X with a 4:1 SYSCLK to INT_FWD_CLK ratio.

Figure 4–5 Fast Transfer Timing Example

SysAddOut_L[14:0] Probe Response

SysData_L[63:0]

D0

D1

D2

D3

D4

D5

D6

SYSCLK

SysAddOutClk_L

INT_FWD_CLK

GCLK

FM05822B.AI4

In fast data mode, movement of data into the 21264/EV67 requires turning around the SysData bus that is being actively driven by the 21264/EV67. Given a SysDc fill com- mand (ReadDataError, ReadData, ReadDataShared, ReadDataShared/Dirty, ReadData- Dirty), the 21264/EV67 responds as follows:

1.Three GCLK cycles after perceiving the SysDc fill command, the 21264/EV67 turns off its drivers, interrupting any ongoing fast data write transactions.

2.The 21264/EV67 drivers stay off until the last piece of fill data is received, or a new SysDc write command overrides the current SysDc fill command. It is the responsi- bility of the external system to schedule SysDc fill or write commands so that there is no conflict on the SysData bus.

3.The 21264/EV67 samples fill data in the GCLK clock domain, 10 +

SYSDC_DELAY GCLK cycles after perceiving the SysDc fill command. The Cbox CSR SYSDC_DELAY[4:0] provides GCLK granularity for precisely placing fills into the processor pipeline discussed in Section 2.2.

4–32Cache and External Interfaces

Alpha 21264/EV67 Hardware Reference Manual

Image 120

Compaq EV67, 21264 specifications Sysclk Cycles Between SysAddOut and SysData, 32Cache and External Interfaces

Contents

Revision/Update Information Alpha 21264A MicroprocessorHardware Reference Manual DS-0028A-TE Alpha 21264/EV67 Hardware Reference Manual Table of Contents Hardware Interface Cache and External Interfaces Internal Processor Registers Privileged Architecture Library Code Initialization and Configuration Mffpcr Mtfpcr Error Detection and Error Handling Testability and DiagnosticsElectrical Data Thermal Management Alpha Instruction Set 21264/EV67 Boundary-Scan Register 21264/EV67-to-Bcache Pin Interconnections Glossary Index Figures Xii Tables Xiv VDD Idcpower Page Content PrefaceAudience Documentation Included by Reference Terminology and Conventions For exampleAbbreviations W1C W1SAddresses Aligned and Unaligned Signal Names Data UnitsDo Not Care External Undefined Do not care. a capital X represents any valid value Page Introduction ArchitectureIntroduction Architecture AddressingInteger Data Types Floating-Point Data Types 21264/EV67 Microprocessor Features 21264/EV67 Microprocessor Features 21264/EV67 Microprocessor Features Internal Architecture 21264/EV67 MicroarchitectureInternal Architecture Instruction Fetch, Issue, and Retire Unit 21264/EV67 MicroarchitectureVirtual Program Counter Logic 21264/EV67 Block Diagram Branch Predictor Local Predictor Global Predictor Choice Predictor Instruction-Stream Translation Buffer Integer Issue Queue Instruction Fetch LogicRegister Rename Maps Floating-Point Issue Queue Hwret Integer Execution Unit Exception and Interrupt LogicRetire Logic PERR, MINxxx, MAXxxx, UNPKxx, PKxx Integer Execution Unit-Clusters 0 Floating-Point Execution Unit 10Internal Architecture External Cache and System Interface Unit Onchip Caches21264/EV67 contains two onchip primary-level caches Memory Reference Unit Data Cache12Internal Architecture Pipeline Organization Pipeline OrganizationSrom Interface Miss address file MAF Dstream translation buffer DTB Stage 0 Instruction Fetch Stage 1 Instruction Slot14Internal Architecture Stage 3 Issue Stage 2 Map Instruction Issue Rules Instruction Issue RulesPipeline Aborts Ebox and Fbox pipelines begin execution Instruction Issue Rules Instruction Group Definitions Instruction Name, Pipeline, and Types Ebox Slotting FTOIS, FtoitITOFS, ITOFF, Itoft Instruction Group Definitions and Pipeline Unit U U L E L U E E L L E U Instruction Issue Rules Instruction Latencies Instruction Class Latency in CyclesHwmfpr 20Internal Architecture Instruction Retire Rules Instruction Retire RulesMinimum Retire Latencies for Instruction Classes Retire of Operate Instructions into R31/F31 Retire of Operate Instructions into R31/F31Floating-Point Divide/Square Root Early Retire BSR/JSR Load Instructions to R31 and F31 Load Instructions to R31 and F31Prefetch with Modify Intent LDS Instruction Instructions Retired Without Execution Special Cases of Alpha Instruction Execution Prefetch with the LDxL / STxC Instruction SequenceLoad Hit Speculation 24Internal Architecture Special Cases of Alpha Instruction Execution Pipeline Timing for Integer Load Instructions Floating-Point Store Instructions Cmov Instruction26Internal Architecture Memory and I/O Address Space Instructions Memory and I/O Address Space InstructionsMemory Address Space Load Instructions 2 I/O Address Space Load Instructions Rules for I/O Address Space Load Instruction Data Merging28Internal Architecture 4 I/O Address Space Store Instructions 8shows some of the following rulesRules for I/O Address Space Store Instruction Data Merging MAF Memory Address Space Merging Rules Instruction OrderingMAF Memory Address Space Merging Rules MAF Merging Rules Replay Traps Replay TrapsMbox Order Traps 10 Memory Reference Ordering 12 I/O Write Buffer and the WMB Instruction Write Buffer and the WMB InstructionOther Mbox Replay Traps Memory Barrier MB/WMB/TB Fill Flow MB Instruction Processing WMB Instruction Processing TB Fill Flow12 TB Fill Flow Example Sequence 34Internal Architecture 13 TB Fill Flow Example Sequence Performance Measurement Support-Performance Counters Floating-Point Control RegisterPerformance Measurement Support-Performance Counters Floating-point control register Fpcr is shown in Figure Floating-Point Control Register Amask and Implver Instruction Values Amask and Implver Instruction ValuesAmask Implver Design Examples Design Examples 13 Typical Multiprocessor Configuration 40Internal Architecture 21264/EV67 Microprocessor Logic Symbol Hardware InterfaceHardware Interface 21264/EV67 Microprocessor Logic Symbol 21264/EV67 Microprocessor Logic Symbol 21264/EV67 Signal Names and Functions 21264/EV67 Signal Names and FunctionsSignal Pin Types Definitions 21264/EV67 Signal Descriptions Dcokh Pllvdd 21264/EV67 Signal Descriptions by Function TestStatH SysVref Domain SysAddInL140 Pin List Sorted by Signal Name Pin AssignmentsPin Assignments AC1 10Hardware Interface Pllvdd AA5 Pin List Sorted by PGA Location 12Hardware Interface SysDataL28 14Hardware Interface BcDataH70 SysDataL5 Ground and Power VSS and VDD Pin List 16Hardware Interface Mechanical Specifications Mechanical Specifications 21264/EV67 Packaging 21264/EV67 Packaging18Hardware Interface 21264/EV67 Bottom View Pin Up Page Cache and External Interfaces Introduction to the External InterfacesCache and External Interfaces Introduction to the External Interfaces System Interface 21264/EV67 System and Bcache Interfaces Commands and Addresses Physical Address ConsiderationsPhysical Address Considerations Second-Level Cache Bcache Interface ECB I/O MB/WMB Physical Address Considerations Bcache Interface Signals Bcache StructureBcache Structure System Duplicate Tag Stores Victim Data Buffer Cache CoherencyVictim Data Buffer Cache Coherency Basics Cache Coherency Cache Block States2lists the cache block states supported by the 21264/EV67 21264/EV67-Supported Cache Block States System Responses to 21264/EV67 Commands Cache Block State TransitionsCache Block State Transitions 10Cache and External Interfaces Cache Coherency Using SysDc Commands 12Cache and External Interfaces Dcache States and Duplicate Tags Lock Mechanism Lock Mechanism14Cache and External Interfaces Internal Eviction of LDxL Blocks Liveness and Fairness System Port System Port16Cache and External Interfaces System Port Pins System Port Pins System Port Programming the System Interface Clocks Programming Values for System Interface ClocksProgram Values for Data-Sample/Drive CSRs 18Cache and External Interfaces 3 21264/EV67-to-System Commands Bank Interleave on Cache Block Boundary ModeForwarded Clocks and Frame Clock Ratio Hit Mode 11 Page Hit Mode of Operation12 21264/EV67-to-System Command Fields Definitions 12describes the field definitions for Tables 4-10and 4 21264/EV67-to-System Commands Descriptions 14describes the 21264/EV67-to-system commands14 21264/EV67-to-System Commands Descriptions 13 Maximum Physical Address for Short Bus Format 22Cache and External Interfaces 15 Programming INVALTODIRTYENABLE10 ProbeResponse Commands Command40 = 16 Programming SETDIRTYENABLE2017 21264/EV67 ProbeResponse Command 24Cache and External Interfaces SysAck and 21264/EV67-to-System Commands Flow Control 18describes the ProbeResponse command fields18 ProbeResponse Fields Descriptions System-to-21264/EV67 Commands Probe Commands Four Cycles19 System-to-21264/EV67 Probe Commands RVB RPB 20 System-to-21264/EV67 Probe Commands Fields Descriptions 21 lists the data movement selected by Probe4322lists the next cache block state selected by Probe20 21 Data Movement Selection by Probe43 Data Transfer Commands Two Cycles 23 Data Transfer Command Format28Cache and External Interfaces 24describes the SysDc40 field 24 SysDc40 Field Description Data Movement In and Out of the 21264/EV67 8.1 21264/EV67 Clock Basics30Cache and External Interfaces Fast Data Mode 25 Sysclk Cycles Between SysAddOut and SysData 32Cache and External Interfaces 26shows four example configurations and shows their use 26 Cbox CSR SYSDCDELAY40 ExamplesFast Data Disable Mode 27 Four Timing Examples SysDataInValidL and SysDataOutValidLSysDataInValidL 34Cache and External Interfaces SysDataOutValidL SysFillValidL Data Wrapping 28 Data Wrapping Rules36Cache and External Interfaces 30defines the interleaved scheme for the wrap order 29 System Wrap and Deliver Data30 Wrap Interleave Order Nonexistent Memory Processing 31defines the wrap order for double-pumped data transfers31 Wrap Order for Double-Pumped Data Transfers 38Cache and External Interfaces 21264/EV67 Command NXM Address System/21264/EV67 Response 10.1 21264/EV67 Commands and System Probes Ordering of System Port Transactions40Cache and External Interfaces System Port Bcache Port Bcache Port Bcache Port Pins 36 Bcache Port Pins35 Range of Maximum Bcache Clock Ratios Bcache Clocking 44Cache and External Interfaces 37 BCCPUCLKDELAY10 Values 38 BCCLKDELAY10 ValuesSetting the Period of the Cache Clock 39 Program Values to Set the Cache Clock Period Single-Data 46Cache and External Interfaces Bcache Transactions 41 Data-Sample/Drive Cbox CSRsBcache Data Read and Tag Read Transactions Bcache Data Write Transactions 48Cache and External Interfaces When the ratio is even, bcfrm is equal to the ratio When the ratio is odd, bcfrm is twice the ratioFor example, in single-data mode Dual-data mode, bcfrm is twice the ratio 50Cache and External Interfaces Pin Descriptions Relationship Between Write-to-Read Bcwrrdbubbles and wrrdRelationship Between Read-to-Write Bcrdwrbubbles and rdwr BcAddH234 44lists the combination of control pin assertion for 46 Control Pin Assertion for Ramtype C 47 Control Pin Assertion for Ramtype DBcDataInClkH and BcTagInClkH Interrupts Interrupts Bcache BankingDisabling the Bcache for Debugging 54Cache and External Interfaces Internal Processor Registers Internal Processor Registers Mbox IPRs Ebox IPRs Ebox IPRsCycle Counter Register CC Cycle Counter Control Register Ccctl Virtual Address Register VA Virtual Address Control Register Vactl2describes the Ccctl register fields Cycle Counter Control Register Fields Description Virtual Address Format Register Vaform 3describes the virtual address control register fieldsVirtual Address Control Register Fields Description VAFORM32 Ibox IPRs Ibox IPRsITB Tag Array Write Register Itbtag ITB PTE Array Write Register Itbpte ITB Invalidate All Process ASM=0 Register Itbiap ITB Invalidate All Register ItbiaITB Invalidate Single Register Itbis Ibox IPRs ProfileMe PC Register Pmpc Exception Address Register Excaddr4describes the ProfileMe PC register fields ProfileMe PC Fields Description Interrupt Enable and Current Processor Mode Register Iercm 13shows Ivaform when ICTLVA48 equals 0 ICTLVAFORM32 equals Software Interrupt Request Register Sirr Iercm Register Fields Description10Internal Processor Registers Interrupt Summary Register Isum 6describes the software interrupt request register fieldsSoftware Interrupt Request Register Fields Description Hardware Interrupt Clear Register Hwintclr 7describes the interrupt summary register fieldsInterrupt Summary Register Fields Description 12Internal Processor Registers Exception Summary Register Excsum 8describes the hardware interrupt clear register fieldsHardware Interrupt Clear Register Fields Description Mchkd W1C 9describes the exception summary register fields Exception Summary Register Fields Description14Internal Processor Registers PAL Base Register Palbase Ibox Control Register Ictl10describes the PAL base register fields 10 PAL Base Register Fields Description 11describes the Ibox control register fields 11 Ibox Control Register Fields Description16Internal Processor Registers Singleissueh MchkenSTWAIT64K PCT1EN Ibox Status Register Istat Spce18Internal Processor Registers 12describes the Ibox status register fields 12 Ibox Status Register Fields DescriptionMIS TRP 20Internal Processor Registers Sleep Mode Register Sleep Ibox IPRs Icache Flush Register IcflushIcache Flush ASM Register Icflushasm Clear Virtual-to-Physical Map Register Clrmap 14describes the process context register fields 14 Process Context Register Fields Description22Internal Processor Registers Performance Counter Control Register Pctrctl FPEPpce 15describes the performance counter control register fields 15 Performance Counter Control Register Fields Description24Internal Processor Registers Mbox IPRs Mbox IPRsDTB Tag Array Write Registers 0 and 1 DTBTAG0, DTBTAG1 16 Performance Counter Control Register Input Select Fields DTB Alternate Processor Mode Register Dtbaltmode 26Internal Processor Registers 17 DTB Alternate Processor Mode Register Fields Description Dstream TB Invalidate All Process ASM=0 Register DtbiapDstream TB Invalidate All Register Dtbia Dstream TB Invalidate Single Registers 0 and 1 DTBIS0,1 Memory Management Status Register Mmstat 18describes the memory management status register fields18 Memory Management Status Register Fields Description 28Internal Processor Registers Mbox Control Register Mctl ForACV Erences to superpages result in access violations Dcache Control Register Dcctl19describes the Mbox control register fields 19 Mbox Control Register Fields Description Dcache Status Register Dcstat 20describes the Dcache control register fields20 Dcache Control Register Fields Description Cbox CSRs and IPRs Cbox CSRs and IPRs21describes the Dcache status register fields 21 Dcache Status Register Fields Description Cbox CSRs and IPRs Cbox Data Register Cdata Cbox Shift Register CshftCbox Writeonce Chain Description 22 describes the Cbox data register fields 24 Cbox Writeonce Chain Order 34Internal Processor Registers Mboxbcprbstall BCLATDATAPATTERN031 BCLATTAGPATTERN023 Skewedfillmode 36Internal Processor Registers SYSCLKDELAY10 Cbox Writemany Chain Description 38Internal Processor Registers 25describes the Cbox Writemany chain order from LSB to MSB 25 Cbox Writemany Chain Order Setdirtyenable = Bcbankenable = 40Internal Processor Registers Cbox CSRs and IPRs Cbox Read Register IPR Description 26 Cbox Read IPR Fields DescriptionPage Privileged Architecture Library Code PALcode DescriptionPrivileged Architecture Library Code PALmode Environment PALmode Environment Required PALcode Function Codes Opcodes Reserved for PALcodeRequired PALcode Function Codes Hwld Instruction Opcodes Reserved for PALcode Hwst Instruction3describes the Hwld instruction fields Hwld Instruction Fields Descriptions Hwret Instruction 4describes the Hwst instruction fieldsHwst Instruction Fields Descriptions Hwmfpr and Hwmtpr Instructions 5describes the Hwret instruction fieldsHwret Instruction Fields Descriptions Hint Internal Processor Register Access Mechanisms Internal Processor Register Access Mechanisms6describes the Hwmfpr and Hwmtpr instructions fields Hwmfpr and Hwmtpr Instructions Fields Descriptions Hardware Structure of Explicitly Written IPRs IPR Access Ordering Paired Instruction Fetch Order 10Privileged Architecture Library Code PALshadow Registers PALcode Emulation of the Fpcr PALcode Entry Points PALcode Exception Entry Points PALcode Exception Entry Locations Translation Buffer TB Fill Flows Translation Buffer TB Fill FlowsDTB Fill 14Privileged Architecture Library Code Wr Data Tb missWr PTE LD-PTE, write TB ITB Fill 16Privileged Architecture Library Code Performance Counter Support Performance Counter Support General Precautions Aggregate Mode Programming GuidelinesAggregate Mode Precautions IPRs Used for Performance Counter Support 10 Aggregate Mode Returned IPR Contents OperationPctrctl SL0 SL1 ProfileMe Mode Programming Guidelines 11shows the counter modes that are used with Aggregate modeThis input counts Mbox replay traps 12 Cmov Decomposed 13 ProfileMe Mode Returned IPR Contents 22Privileged Architecture Library Code ProfileMe Counting Mode Description Cycle counting Inum retire delay cycles 14shows the counter modes that are used with ProfileMe mode Counter Modes for ProfileMe Mode14 ProfileMe Mode Pctrctl Input Select Fields 24Privileged Architecture Library Code Initialization and Configuration Power-Up Reset Flow and the ResetL and Dcokh Pins21264/EV67 Reset State Machine Major Operations Initialization and Configuration Power-Up Reset Flow and the ResetL and Dcokh Pins Constraints Power Sequencing and Reset State for Signal Pins Signal Pin Reset State Clock Forwarding and System Clock Ratio Configuration Pllvdd Pin Signal Names and Initialization State PLL PLL Ramp Up BiST and Srom Load and the TestStatH Pin Clock Forward Reset and System Interface Initialization Power-Up Flow Signals and Their Constraints Fault Reset Flow Fault Reset FlowEffect on IPRs After Fault Reset Energy Star Certification and Sleep Mode Flow Energy Star Certification and Sleep Mode Flow Effect on IPRs After Transition Through Sleep Mode 10Initialization and Configuration Warm Reset Flow Warm Reset FlowSignals and Constraints for the Sleep Mode Sequence Effect on IPRs After Warm Reset Initialization Mode Processing 12Initialization and ConfigurationArray Initialization Array Initialization Initialization Mode Processing EVICTENABLE0 Internal Processor Register Power-Up Reset State 10 Internal Processor Registers at Power-Up Reset State14Initialization and Configuration External Interface Initialization Internal Processor Register Power-Up Reset State Ieee 1149.1 Test Port Reset Reset State MachineIeee 1149.1 Test Port Reset 16Initialization and Configuration Reset State Machine 11 21264/EV67 Reset State Machine State Descriptions 18Initialization and Configuration Phase-Lock Loop PLL Functional Description Phase-Lock Loop PLL Functional DescriptionDifferential Reference Clocks PLL Output Clocks Power-Up/Reset Clocking 20Initialization and Configuration Error Detection and Error Handling 21264/EV67 Error Detection MechanismsError Detection and Error Handling Data Error Correction Code Icache Data or Tag Parity ErrorDcache Tag Parity Error Data Error Correction Code Dcache Data Single-Bit Correctable ECC Error Dcache Data Single-Bit Correctable ECC ErrorLoad Instruction Dcache Store Second Error Dcache Duplicate Tag Parity ErrorDcache Store Second Error Store Instruction Quadword or Smaller Bcache Tag Parity Error Bcache Data Single-Bit Correctable ECC ErrorBcache Tag Parity Error Icache Fill from Bcache Bcache Victim Read Bcache Victim Read During a Dcache/Bcache Miss Memory/System Port Single-Bit Data Correctable ECC Error Memory/System Port Single-Bit Data Correctable ECC ErrorIcache Fill from Memory Dcache Fill from Memory Bcache Data Single-Bit Correctable ECC Error on a Probe Bcache Data Single-Bit Correctable ECC Error on a Probe Double-Bit Fill Errors Error Case SummaryDouble-Bit Fill Errors 3summarizes the various error cases and their ramifications Error Case Summary 10Error Detection and Error Handling Mchk Cstatdstreambcdbl Mchk CstatistreammemdblMchk Cstatdstreammemdbl Page Electrical Characteristics Electrical Data1lists the maximum electrical ratings for the 21264/EV67 Maximum Electrical Ratings DC Characteristics DC CharacteristicsSignal Types Idcpower VDD Idcpower Input DC Reference Pin IdcrefInput Differential Amplifier Receiver IDA Input Differential Amplifier Clock Receiver Idaclk Pin Type Open-Drain Driver for Test Pins Oodtp Pin Type Open-Drain Output Driver OODIOZ Codtp 11 Push-Pull Output Driver OPP 12 Push-Pull Output Clock Driver Oppclk AC Characteristics AC CharacteristicsAC Test Conditions 13 AC Specifications TSU TDH TSU1 TDH2 AC Characteristics Page Operating Temperature Ambient temperature requirementOperating Temperature at Heat Sink Center Tc Thermal Management Operating Temperature Θca at Various Airflows for 21264/EV6710-2Thermal Management Heat Sink Specifications Heat Sink Specifications Type 1 Heat Sink 10-4Thermal Management Type 2 Heat Sink Type 3 Heat Sink 10-6Thermal Management Thermal Design Considerations Thermal Design ConsiderationsPage Testability and Diagnostics Test PinsDedicated Test Port Pins Testability and Diagnostics SROM/Serial Diagnostic Terminal Port SROM/Serial Diagnostic Terminal Port11-2Testability and Diagnostics Srom Load Operation Ieee 1149.1 Port Ieee 1149.1 PortIeee 1149.1 Instructions and Opcodes 11-4Testability and Diagnostics TestStatH PinTestStatH Pin Power-Up Self-Test and Initialization Power-Up Self-Test and InitializationBuilt-in Self-Test Srom Initialization 11-6Testability and Diagnostics Serial Instruction Cache Load Operation See Appendix B for a listing of the Boundary-Scan Register Icache Bit Fields in an Srom LineReferences Page Alpha Instruction Set Alpha Instruction SummaryTable A-1 Instruction Format and Opcode Notation Alpha Instruction Set A-1 Alpha Instruction Summary Mbr Branch to subroutine Pcd Trap to PALcodeOpr 11.24 Cmove if = zero Opr 11.46 Cmove if ≥ zero 15.0AF Convert Gfloating to quadword 17.010 Convert longword to quadword15.0BC Convert quadword to Ffloating 15.0BE Convert quadword to Gfloating 17.02F Fcmove if zero 17.02E Fcmove if ≤ zero17.02C Fcmove if zero 17.02B Fcmove if ≠ zero Opr 13.40 Multiply longword with integer overflow enable Opr 13.60 Multiply quadword with integer overflow enableOpr 1C.31 Pixel error Mem Load Sfloating Opr 1C.36 Pack words to bytes Mfc 18.E000 Read and clear Mbr 1A.2 Return from subroutineMfc 18.C000 Read process cycle counter 18.F000 Read and set Opr 10.02 Scaled add longword by Reserved Opcodes Reserved OpcodesOpcodes Reserved for Compaq Ieee Floating-Point Instructions Ieee Floating-Point Instructions VAX Floating-Point Instructions Independent Floating-Point InstructionsVAX Floating-Point Instructions Opcode Summary Opcode Summary Mem Table A-9explains the symbols used in Table A-8 Mem ResIeee floating-point instruction opcodes Floating-point operate instruction opcodes Ieee Floating-Point Conformance Ieee Floating-Point Conformance14Alpha Instruction Set Table A-11 Exceptional Input and Output Conditions Alpha Instruction Set A-15 Cmpteq Cmptun Input Cmptlt Cmptle Input16Alpha Instruction Set Fbeq Fbne Fblt Fble Fbgt Fbge LDS LDT STS STT Cpys Cpysn Alpha Instruction Set A-17Page 21264/EV67 Boundary-Scan Register Boundary-Scan Register Boundary-Scan Register Pllvdd 21264/EV67 Boundary-Scan Register B-3 421264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B-5 621264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B-7 821264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B-9 1021264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B-11 1221264/EV67 Boundary-Scan Register Serial Icache Load Predecode Values Serial Icache Load Predecode Values C-1Page PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-1 2PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-3 4PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-5 Initwritemany 6PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-7 8PALcode Restrictions and Guidelines Restriction 7 Replay Trap, Interrupt Code Sequence, and STF PALcode Restrictions and Guidelines D-9 Restriction 10 Duplicate IPR Mode Bits Restriction 9 PALmode Istream Address RangesRestriction 9 PALmode Istream Address Ranges 10PALcode Restrictions and Guidelines Restriction 11 Ibox IPR Update Synchronization Restriction 11 Ibox IPR Update SynchronizationRestriction 13 DTB Fill Flow Collision Restriction 14 Hwret Guideline 20 Ictlsbe Stream Buffer Enable Guideline 16 JSR-BAD VARestriction 21 HWRET/STALL After Hwmtpr ASN0/ASN1 Guideline 16 JSR-BAD VA Restriction 22 HWRET/STALL After Hwmtpr IS0/IS1 Restriction 22 HWRET/STALL After Hwmtpr IS0/IS1PALcode Restrictions and Guidelines D-13 Restriction 25 Hwmtpr Itbia After Reset Guideline 26 Conditional Branches in PALcodeRestriction 24 HWRET/STALL After Hwmtpr ICFLUSH, Icflushasm 14PALcode Restrictions and Guidelines Guideline 29 JSR, JMP, RET, and Jsrcor in PALcode Restriction 30 Hwmtpr and Hwmfpr to the Cbox CSRPALcode Restrictions and Guidelines D-15 Restriction 30 Hwmtpr and Hwmfpr to the Cbox CSR 16PALcode Restrictions and Guidelines Restriction 31 ICTLVA48 Update Restriction 32 Pctrctl UpdateRestriction 31 ICTLVA48 Update PALcode Restrictions and Guidelines D-17 Guideline 35 Hwintclr Update Restriction 33 Hwld Physical/Lock UseRestriction 36 Updating Ictlsde Restriction 37 Updating VACTLVA48 Restriction 40 Scrubbing a Single-Bit Error PALcode Restrictions and Guidelines D-19 Restriction 40 Scrubbing a Single-Bit Error 20PALcode Restrictions and Guidelines Restriction 42 Updating VACTL, CCCTL, or CC IPRs Restriction 43 No Trappable Instructions Along withPALcode Restrictions and Guidelines D-21 Restriction 47 Cache Eviction for Single-Bit Cache Errors 22PALcode Restrictions and Guidelines Restriction 47 Cache Eviction for Single-Bit Cache Errors PALcode Restrictions and Guidelines D-23 24PALcode Restrictions and Guidelines 21264/EV67-to-Bcache Pin Interconnections Forwarding Clock Pin GroupingsTable E-1 Bcache Forwarding Clock Pin Groupings Late-Write Non-Bursting SSRAMs Late-Write Non-Bursting SSRAMsData Pin Usage Tag Pin Usage Dual-Data Rate SSRAMs Dual-Data Rate SSRAMsData and Tag Pin Usage Table E-4 Dual-Data Rate Ssram Data Pin Usage Trstl Table E-5 Dual-Data Rate Ssram Tag Pin Usage Glossary BIU BSR Cisc Cmos CPICPU CSR DMA DramDTB DTL Feprom FETFEU Fpga Gclk IDU Iowb IpgaITB Jfet MAF MBOMBZ Mips MSI Naturally AlignedNmos Nvram PAL PGAPLA Plcc Pqfp PromRAM RAS Risc ROMRTL SAM Sdram SimmSIP Sipp Stram TTLUart Unaligned Unpredictable UvpromVAF VDF WAR Writeblock Index Numerics Index-2 Index-3 Index-4 ECC Index-6 Index-7 Index-8 Index-9 Index-10 Index-11 Index-12