Compaq 21264, EV67 specifications Design Examples

Design Examples

2.16 Design Examples

The 21264/EV67 can be designed into many different uniprocessor and multiprocessor system configurations. Figures 2–12and 2–13illustrate two possible configurations. These configurations employ additional system/memory controller chipsets.

Figure 2–12shows a typical uniprocessor system with a second-level cache. This sys- tem configuration could be used in standalone or networked workstations.

Figure 2–12 Typical Uniprocessor Configuration

L2 Cache	21264
Tag	Tag
Store
	Address
	Out
	Address
	Address
	In
Data	Data
Store
	Data

21272 Core Logic Chipset

Control

Chips

Data Slice

Chips

Host PCI

Bridge Chip

64-bit PCI Bus

Duplicate

Tag Store

(Optional)

DRAM

Arrays

Address

Data

FM-05573-EV67

Figure 2–13shows a typical multiprocessor system, each processor with a second-level cache. Each interface controller must employ a duplicate tag store to maintain cache coherency. This system configuration could be used in a networked database server application.

Alpha 21264/EV67 Hardware Reference Manual Internal Architecture 2–39