Compaq 21264, EV67 6.8 PALcode Entry Points

6–12 Privileged Architecture Library Code

Alpha 21264/EV67 Hardware Reference Manual

3. Correct actions must occur when the FPCR is written by way of a MT_FPCR

instruction.

The FPCR status bits in the 21264/EV67 are set with PALcode assistance. Floating-

point exceptions, for which the associate d FPCR status bit is clear or for which the

associated trap is enabled, result in a hardware trap to the ARITH P ALcode routin e. The

EXC_SUM register contains information to allow t his routine to update the FPCR

appropriately, and to decide whether to report the exception to the operating system.

The MF_FPCR is issued from the floating-point queue and executed by the Fbox. No

PALcode assistance is required.

The MT_FPCR instruction is issued from the floating-point queue. This instruction is

implemented as an explicit IPR write o peration. The value is written into t he first latch,

and when the instruction is retired, the value is writ ten into the second latch. There is no

IPR scoreboarding mechanism in the floating-point queue, so PALcode assistance is

required to ensure that subsequent readers of the FPCR get the updated value.

After writing the first latch, the MT_FPCR instruction invokes a synchronous trap to

the MT_FPCR PALcode entry point. The PALcode can return using a HW_RET

instruction with its STALL bit set. This sequence ensures that the MT_FPCR instruc-

tion will be correctly ordered for subseque nt readers of the FPCR.

6.8 PALcode Entry Points

PALcode is invoked at specific entry points, of which there are two classes:

CALL_PAL and exceptions.

CALL_PAL entry points are used whenever the Ibox encounters a CALL_PAL instruc-

tion in the Istream. To speed the processing of CALL_PAL instructions, CALL_PAL

instructions do not invoke pipeline aborts but are processed as normal jumps to the off-

set from the contents of the PAL_BASE register, which i s specified by the CALL_PAL

instruction’s function field.

The Ibox fetches a CALL_PAL instruction, bubbles one cycle, and then fetches the

instructions at the CALL_PAL entry point. For convenience of implemen tation, retur ns

from CALL_PAL are aided by a linkage register (much like JSRs). PALshadow regis-

ter R23 is used as the linkage register. The Ibox loads the PC of the instruction after the

CALL_PAL instruction, into the linkage register. Bit [0] of the linkag e register is set if

the CALL_PAL instruction was executed while the processor was in PALmode.

The Ibox pushes the value of the return PC onto the re turn prediction stack.

CALL_PAL instructions start at the following offsets:

•Privileged CALL_PAL instructions start at offset 200016.

•Nonprivileged CALL_PAL instructions start at offset 300016.