Compaq 21264, EV67 specifications Clock Forward Reset and System Interface Initialization

Power-Up Reset Flow and the Reset_L and DCOK_H Pins

As BiST completes, the TestStat_H pin is held low for 16 GCLK cycles. Then, if BiST succeeds, the pin remains low. Otherwise, it is asserted. After successfully completing BiST, the 21264/EV67 then performs the SROM load sequence (described in Chapter 11). After the SROM load sequence is finished, the 21264/EV67 deasserts SromOE_L.

7.1.5 Clock Forward Reset and System Interface Initialization

After the deassertion of SromOE_L, the reset state machine enters the

WAIT_ClkFwdRst1 state, where the 21264/EV67 waits for the system to deassert ClkFwdReset_H. The 21264/EV67 samples the deasserting edge of ClkFwdReset_H to take synchronous actions. It uses this synchronous event to reset the clock forward- ing interface, start the outgoing clocks, and deassert internal reset. The chip then waits 264 cycles before issuing commands. The reset state machine is then in RUN and the 21264/EV67 begins fetching code at address 0x780.

Table 7–4lists signals relevant to the power-up flow, provides a short description of each, and any relevant constraints.

Table 7–4 Power-Up Flow Signals and Their Constraints

Signal Name Description Constraint

ClkIn_x	Differential clocks that are
	inputs to PLL or are
	bypassed onto GCLK
	directly

Clocks must be running before DCOK_H is asserted.

PLL_VDD	VDD supply to PLL
VDD	VDD supply to the 21264/
	EV67 chip logic (except
	PLL)
DCOK_H	Logic signal to the 21264/
	EV67 that the VDD supply
	is good
Reset_L	RESET pin asserted by
	SYSTEM to the 21264/
	EV67

PLL_VDD must lead VDD.

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Reset_L must be asserted prior to DCOK_H and must remain asserted for at least 100 ms after DCOK_H is asserted. This allows for PLL settling time. Deassertion of Reset_L causes the 21264/ EV67 to ramp divisors to their final value and begin BiST.

ClkFwdRst_H	Signal asserted by SYS-
Deassertion #1	TEM to synchronously
	commence built-in self-test
	and SROM load

ClkFwdRst_H must be deasserted after PLL has achieved its lock in its final divisor value (about 20 μs). The deassertion causes built-in self-test to begin on an internal clock cycle that corresponds to one framing clock cycle after ClkFwdRst_H is deasserted. ClkFwdRst_H can be asserted after one frame clock cycle. See Figure 7–1.

ClkFwdRst_H	Signal asserted by SYS-
Deassertion #2	TEM to initialize and reset
	clock forwarding interfaces

ClkFwdRst_H must be deasserted when the Cbox has loaded configuration information. This occurs as the first part of the serial ROM load, after BiST is run. Once ClkFwdRst_H is deasserted, the interface is initialized and can receive probe requests from the 21264/EV67.

Alpha 21264/EV67 Hardware Reference Manual Initialization and Configuration 7–7