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Compaq 21264, EV67 Operation, Pctrctl SL0, SL1, Ictl Spce, Aggregate Mode Returned IPR Contents

Models: 21264 EV67

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Performance Counter Support

The legal range for PCTR0 when writing the IPR is 0:(2**20-16).

The legal range for PCTR1 when writing the IPR is 0:(2**20-4).

6.10.2.2Operation

1.Setup

The following IPRs need to be set up by PALcode instructions.

IPR Name	Relevant Fields		Meaning

IER_CM	PCEN[1:0]		Enable Interrupts.
PCTX	PPCE		Enable Process Performance Counting or use I_CTL[SPCE].
PCTR_CTL	SL0		Selects Aggregate or ProfileMe mode; set to 0 for Aggregate mode.
	SL1		Selects PCTR0 and PCTR1 counting modes. See Table 6–11for more infor-
			mation.
	PCTR0[19:0]		Set counter 0 starting value [0:(2**20-16)]. See Section 6.10.1 for setup
			precautions.
	PCTR1[19:0]		Set counter 1 starting value [0:(2**20-4)]. See Section 6.10.1 for setup pre-
			cautions.
I_CTL	SPCE		Enable System Performance Counting or use PCTX[PPCE].
	PCT0_EN		Enable performance counter 0.
	PCT1_EN		Enable performance counter 1.

	2.	Count
		If PCTR0 and PCTR1 are enabled, will increment according to modes selected by
		SL0 and SL1.
	3.	Overflow
		If PCEN[1:0] is enabled, PC[1:0] is set when PCTR0 or PCTR1 overflows.
	4.	Hardware interrrupt

When PC[1:0] is set, the PALcode interrupt routine is entered. Interrupt is acknowl- edged and PALcode generates an interrupt to the operating system performance monitoring utility.

5. Operating system interrupt handler

The handler should read the IPR PCTR_CTL, as shown in Table 6–10,to note which counter overflowed in the handler's data structures. The handler may read the counter to see how many events have happened since the overflow.

The handler may also choose to write the counters to control the frequency of inter- rupts.

Table 6–10 Aggregate Mode Returned IPR Contents

IPR	Field	Contents

PCTR_CTL	PCTR0[19:0]	Counter #0 value
	PCTR1[19:0]	Counter #1 value

Alpha 21264/EV67 Hardware Reference Manual

Privileged Architecture Library Code 6–19

Image 203

Compaq 21264, EV67 specifications Operation, Pctrctl SL0, SL1, Ictl Spce, Aggregate Mode Returned IPR Contents

Contents

DS-0028A-TE Revision/Update InformationAlpha 21264A Microprocessor Hardware Reference ManualAlpha 21264/EV67 Hardware Reference Manual Table of Contents Cache and External Interfaces Hardware InterfaceInternal Processor Registers Privileged Architecture Library Code Mffpcr Mtfpcr Initialization and ConfigurationThermal Management Error Detection and Error HandlingTestability and Diagnostics Electrical Data21264/EV67 Boundary-Scan Register Alpha Instruction SetGlossary Index 21264/EV67-to-Bcache Pin InterconnectionsFigures Xii Tables Xiv VDD Idcpower Page Audience ContentPreface Documentation Included by Reference Abbreviations Terminology and ConventionsFor example Aligned and Unaligned W1CW1S AddressesExternal Signal NamesData Units Do Not CareUndefined Do not care. a capital X represents any valid value Page Introduction IntroductionArchitecture Floating-Point Data Types ArchitectureAddressing Integer Data Types21264/EV67 Microprocessor Features 21264/EV67 Microprocessor Features21264/EV67 Microprocessor Features Internal Architecture Internal Architecture21264/EV67 Microarchitecture Virtual Program Counter Logic Instruction Fetch, Issue, and Retire Unit21264/EV67 Microarchitecture Branch Predictor 21264/EV67 Block DiagramGlobal Predictor Local PredictorInstruction-Stream Translation Buffer Choice PredictorRegister Rename Maps Integer Issue QueueInstruction Fetch Logic Hwret Floating-Point Issue QueueRetire Logic Integer Execution UnitException and Interrupt Logic Integer Execution Unit-Clusters 0 PERR, MINxxx, MAXxxx, UNPKxx, PKxx10Internal Architecture Floating-Point Execution Unit21264/EV67 contains two onchip primary-level caches External Cache and System Interface UnitOnchip Caches 12Internal Architecture Memory Reference UnitData Cache Miss address file MAF Dstream translation buffer DTB Pipeline OrganizationPipeline Organization Srom Interface14Internal Architecture Stage 0 Instruction FetchStage 1 Instruction Slot Stage 2 Map Stage 3 IssueEbox and Fbox pipelines begin execution Instruction Issue RulesInstruction Issue Rules Pipeline AbortsInstruction Name, Pipeline, and Types Instruction Issue Rules Instruction Group DefinitionsInstruction Group Definitions and Pipeline Unit Ebox SlottingFTOIS, Ftoit ITOFS, ITOFF, ItoftU U L E L U E E L L E U 20Internal Architecture Instruction Issue Rules Instruction LatenciesInstruction Class Latency in Cycles HwmfprMinimum Retire Latencies for Instruction Classes Instruction Retire RulesInstruction Retire Rules BSR/JSR Retire of Operate Instructions into R31/F31Retire of Operate Instructions into R31/F31 Floating-Point Divide/Square Root Early RetireInstructions Retired Without Execution Load Instructions to R31 and F31Load Instructions to R31 and F31 Prefetch with Modify Intent LDS Instruction24Internal Architecture Special Cases of Alpha Instruction ExecutionPrefetch with the LDxL / STxC Instruction Sequence Load Hit SpeculationPipeline Timing for Integer Load Instructions Special Cases of Alpha Instruction Execution26Internal Architecture Floating-Point Store InstructionsCmov Instruction Memory Address Space Load Instructions Memory and I/O Address Space InstructionsMemory and I/O Address Space Instructions 28Internal Architecture 2 I/O Address Space Load InstructionsRules for I/O Address Space Load Instruction Data Merging Rules for I/O Address Space Store Instruction Data Merging 4 I/O Address Space Store Instructions8shows some of the following rules MAF Merging Rules MAF Memory Address Space Merging RulesInstruction Ordering MAF Memory Address Space Merging Rules10 Memory Reference Ordering Replay TrapsReplay Traps Mbox Order TrapsMemory Barrier MB/WMB/TB Fill Flow 12 I/O Write Buffer and the WMB InstructionWrite Buffer and the WMB Instruction Other Mbox Replay TrapsMB Instruction Processing 34Internal Architecture WMB Instruction ProcessingTB Fill Flow 12 TB Fill Flow Example Sequence13 TB Fill Flow Example Sequence Floating-point control register Fpcr is shown in Figure Performance Measurement Support-Performance CountersFloating-Point Control Register Performance Measurement Support-Performance CountersFloating-Point Control Register Implver Amask and Implver Instruction ValuesAmask and Implver Instruction Values AmaskDesign Examples Design Examples40Internal Architecture 13 Typical Multiprocessor ConfigurationHardware Interface 21264/EV67 Microprocessor Logic SymbolHardware Interface 21264/EV67 Microprocessor Logic Symbol 21264/EV67 Microprocessor Logic Symbol21264/EV67 Signal Descriptions 21264/EV67 Signal Names and Functions21264/EV67 Signal Names and Functions Signal Pin Types DefinitionsDcokh Pllvdd TestStatH 21264/EV67 Signal Descriptions by FunctionSysVref Domain SysAddInL140 Pin Assignments Pin List Sorted by Signal NamePin Assignments AC1 Pllvdd 10Hardware InterfaceAA5 12Hardware Interface Pin List Sorted by PGA LocationSysDataL28 14Hardware Interface BcDataH70 SysDataL5 16Hardware Interface Ground and Power VSS and VDD Pin ListMechanical Specifications Mechanical Specifications18Hardware Interface 21264/EV67 Packaging21264/EV67 Packaging 21264/EV67 Bottom View Pin Up Page Cache and External Interfaces Cache and External InterfacesIntroduction to the External Interfaces Introduction to the External Interfaces 21264/EV67 System and Bcache Interfaces System InterfaceSecond-Level Cache Bcache Interface Commands and AddressesPhysical Address Considerations Physical Address ConsiderationsMB/WMB ECB I/OPhysical Address Considerations System Duplicate Tag Stores Bcache Interface SignalsBcache Structure Bcache StructureCache Coherency Basics Victim Data BufferCache Coherency Victim Data Buffer21264/EV67-Supported Cache Block States Cache CoherencyCache Block States 2lists the cache block states supported by the 21264/EV6710Cache and External Interfaces System Responses to 21264/EV67 CommandsCache Block State Transitions Cache Block State TransitionsCache Coherency Using SysDc Commands 12Cache and External Interfaces Dcache States and Duplicate Tags 14Cache and External Interfaces Lock MechanismLock Mechanism Liveness and Fairness Internal Eviction of LDxL Blocks16Cache and External Interfaces System PortSystem Port System Port Pins System Port Pins18Cache and External Interfaces System Port Programming the System Interface ClocksProgramming Values for System Interface Clocks Program Values for Data-Sample/Drive CSRsForwarded Clocks and Frame Clock Ratio 3 21264/EV67-to-System CommandsBank Interleave on Cache Block Boundary Mode 12describes the field definitions for Tables 4-10and Hit Mode11 Page Hit Mode of Operation 12 21264/EV67-to-System Command Fields Definitions13 Maximum Physical Address for Short Bus Format 4 21264/EV67-to-System Commands Descriptions14describes the 21264/EV67-to-system commands 14 21264/EV67-to-System Commands Descriptions22Cache and External Interfaces 15 Programming INVALTODIRTYENABLE10 24Cache and External Interfaces ProbeResponse Commands Command40 =16 Programming SETDIRTYENABLE20 17 21264/EV67 ProbeResponse Command18 ProbeResponse Fields Descriptions SysAck and 21264/EV67-to-System Commands Flow Control18describes the ProbeResponse command fields RVB RPB System-to-21264/EV67 CommandsProbe Commands Four Cycles 19 System-to-21264/EV67 Probe Commands21 Data Movement Selection by Probe43 20 System-to-21264/EV67 Probe Commands Fields Descriptions21 lists the data movement selected by Probe43 22lists the next cache block state selected by Probe2028Cache and External Interfaces Data Transfer Commands Two Cycles23 Data Transfer Command Format 24 SysDc40 Field Description 24describes the SysDc40 field30Cache and External Interfaces Data Movement In and Out of the 21264/EV678.1 21264/EV67 Clock Basics Fast Data Mode 32Cache and External Interfaces 25 Sysclk Cycles Between SysAddOut and SysDataFast Data Disable Mode 26shows four example configurations and shows their use26 Cbox CSR SYSDCDELAY40 Examples 34Cache and External Interfaces 27 Four Timing ExamplesSysDataInValidL and SysDataOutValidL SysDataInValidLSysFillValidL SysDataOutValidL36Cache and External Interfaces Data Wrapping28 Data Wrapping Rules 30 Wrap Interleave Order 30defines the interleaved scheme for the wrap order29 System Wrap and Deliver Data 38Cache and External Interfaces Nonexistent Memory Processing31defines the wrap order for double-pumped data transfers 31 Wrap Order for Double-Pumped Data Transfers21264/EV67 Command NXM Address System/21264/EV67 Response 40Cache and External Interfaces 10.1 21264/EV67 Commands and System ProbesOrdering of System Port Transactions System Port Bcache Port Bcache Port35 Range of Maximum Bcache Clock Ratios Bcache Port Pins36 Bcache Port Pins 44Cache and External Interfaces Bcache ClockingSetting the Period of the Cache Clock 37 BCCPUCLKDELAY10 Values38 BCCLKDELAY10 Values 46Cache and External Interfaces 39 Program Values to Set the Cache Clock Period Single-DataBcache Data Read and Tag Read Transactions Bcache Transactions41 Data-Sample/Drive Cbox CSRs 48Cache and External Interfaces Bcache Data Write TransactionsDual-data mode, bcfrm is twice the ratio When the ratio is even, bcfrm is equal to the ratioWhen the ratio is odd, bcfrm is twice the ratio For example, in single-data mode50Cache and External Interfaces BcAddH234 Pin DescriptionsRelationship Between Write-to-Read Bcwrrdbubbles and wrrd Relationship Between Read-to-Write Bcrdwrbubbles and rdwr44lists the combination of control pin assertion for BcDataInClkH and BcTagInClkH 46 Control Pin Assertion for Ramtype C47 Control Pin Assertion for Ramtype D 54Cache and External Interfaces InterruptsInterrupts Bcache Banking Disabling the Bcache for DebuggingInternal Processor Registers Internal Processor RegistersMbox IPRs Cycle Counter Control Register Ccctl Ebox IPRsEbox IPRs Cycle Counter Register CCCycle Counter Control Register Fields Description Virtual Address Register VAVirtual Address Control Register Vactl 2describes the Ccctl register fieldsVAFORM32 Virtual Address Format Register Vaform3describes the virtual address control register fields Virtual Address Control Register Fields DescriptionITB PTE Array Write Register Itbpte Ibox IPRsIbox IPRs ITB Tag Array Write Register ItbtagITB Invalidate Single Register Itbis ITB Invalidate All Process ASM=0 Register ItbiapITB Invalidate All Register Itbia ProfileMe PC Fields Description Ibox IPRs ProfileMe PC Register PmpcException Address Register Excaddr 4describes the ProfileMe PC register fields13shows Ivaform when ICTLVA48 equals 0 ICTLVAFORM32 equals Interrupt Enable and Current Processor Mode Register Iercm10Internal Processor Registers Software Interrupt Request Register SirrIercm Register Fields Description Software Interrupt Request Register Fields Description Interrupt Summary Register Isum6describes the software interrupt request register fields 12Internal Processor Registers Hardware Interrupt Clear Register Hwintclr7describes the interrupt summary register fields Interrupt Summary Register Fields DescriptionMchkd W1C Exception Summary Register Excsum8describes the hardware interrupt clear register fields Hardware Interrupt Clear Register Fields Description14Internal Processor Registers 9describes the exception summary register fieldsException Summary Register Fields Description 10 PAL Base Register Fields Description PAL Base Register PalbaseIbox Control Register Ictl 10describes the PAL base register fields16Internal Processor Registers 11describes the Ibox control register fields11 Ibox Control Register Fields Description PCT1EN SingleissuehMchken STWAIT64K18Internal Processor Registers Ibox Status Register IstatSpce TRP 12describes the Ibox status register fields12 Ibox Status Register Fields Description MIS20Internal Processor Registers Clear Virtual-to-Physical Map Register Clrmap Sleep Mode Register SleepIbox IPRs Icache Flush Register Icflush Icache Flush ASM Register Icflushasm22Internal Processor Registers 14describes the process context register fields14 Process Context Register Fields Description Ppce Performance Counter Control Register PctrctlFPE 24Internal Processor Registers 15describes the performance counter control register fields15 Performance Counter Control Register Fields Description 16 Performance Counter Control Register Input Select Fields Mbox IPRsMbox IPRs DTB Tag Array Write Registers 0 and 1 DTBTAG0, DTBTAG126Internal Processor Registers DTB Alternate Processor Mode Register DtbaltmodeDstream TB Invalidate Single Registers 0 and 1 DTBIS0,1 17 DTB Alternate Processor Mode Register Fields DescriptionDstream TB Invalidate All Process ASM=0 Register Dtbiap Dstream TB Invalidate All Register Dtbia28Internal Processor Registers Memory Management Status Register Mmstat18describes the memory management status register fields 18 Memory Management Status Register Fields DescriptionACV Mbox Control Register MctlFor 19 Mbox Control Register Fields Description Erences to superpages result in access violationsDcache Control Register Dcctl 19describes the Mbox control register fields20 Dcache Control Register Fields Description Dcache Status Register Dcstat20describes the Dcache control register fields 21 Dcache Status Register Fields Description Cbox CSRs and IPRsCbox CSRs and IPRs 21describes the Dcache status register fields22 describes the Cbox data register fields Cbox CSRs and IPRs Cbox Data Register CdataCbox Shift Register Cshft Cbox Writeonce Chain Description34Internal Processor Registers 24 Cbox Writeonce Chain OrderSkewedfillmode Mboxbcprbstall BCLATDATAPATTERN031 BCLATTAGPATTERN02336Internal Processor Registers SYSCLKDELAY10 38Internal Processor Registers Cbox Writemany Chain Description25 Cbox Writemany Chain Order 25describes the Cbox Writemany chain order from LSB to MSB40Internal Processor Registers Setdirtyenable = Bcbankenable =26 Cbox Read IPR Fields Description Cbox CSRs and IPRs Cbox Read Register IPR DescriptionPage Privileged Architecture Library Code Privileged Architecture Library CodePALcode Description PALmode Environment PALmode EnvironmentHwld Instruction Required PALcode Function CodesOpcodes Reserved for PALcode Required PALcode Function CodesHwld Instruction Fields Descriptions Opcodes Reserved for PALcodeHwst Instruction 3describes the Hwld instruction fieldsHwst Instruction Fields Descriptions Hwret Instruction4describes the Hwst instruction fields Hint Hwmfpr and Hwmtpr Instructions5describes the Hwret instruction fields Hwret Instruction Fields DescriptionsHwmfpr and Hwmtpr Instructions Fields Descriptions Internal Processor Register Access MechanismsInternal Processor Register Access Mechanisms 6describes the Hwmfpr and Hwmtpr instructions fieldsHardware Structure of Explicitly Written IPRs Paired Instruction Fetch Order IPR Access Ordering10Privileged Architecture Library Code PALcode Emulation of the Fpcr PALshadow RegistersPALcode Entry Points PALcode Exception Entry Locations PALcode Exception Entry Points14Privileged Architecture Library Code Translation Buffer TB Fill FlowsTranslation Buffer TB Fill Flows DTB FillWr PTE LD-PTE, write TB Wr DataTb miss 16Privileged Architecture Library Code ITB FillPerformance Counter Support Performance Counter SupportIPRs Used for Performance Counter Support General PrecautionsAggregate Mode Programming Guidelines Aggregate Mode PrecautionsSL1 10 Aggregate Mode Returned IPR ContentsOperation Pctrctl SL0This input counts Mbox replay traps ProfileMe Mode Programming Guidelines11shows the counter modes that are used with Aggregate mode 12 Cmov Decomposed 22Privileged Architecture Library Code 13 ProfileMe Mode Returned IPR ContentsInum retire delay cycles ProfileMe Counting Mode Description Cycle counting24Privileged Architecture Library Code 14shows the counter modes that are used with ProfileMe modeCounter Modes for ProfileMe Mode 14 ProfileMe Mode Pctrctl Input Select FieldsInitialization and Configuration Initialization and ConfigurationPower-Up Reset Flow and the ResetL and Dcokh Pins 21264/EV67 Reset State Machine Major OperationsConstraints Power-Up Reset Flow and the ResetL and Dcokh PinsSignal Pin Reset State Power Sequencing and Reset State for Signal PinsPllvdd Clock Forwarding and System Clock Ratio ConfigurationPLL Pin Signal Names and Initialization StateBiST and Srom Load and the TestStatH Pin PLL Ramp UpPower-Up Flow Signals and Their Constraints Clock Forward Reset and System Interface InitializationEffect on IPRs After Fault Reset Fault Reset FlowFault Reset Flow Energy Star Certification and Sleep Mode Flow Energy Star Certification and Sleep Mode Flow10Initialization and Configuration Effect on IPRs After Transition Through Sleep ModeEffect on IPRs After Warm Reset Warm Reset FlowWarm Reset Flow Signals and Constraints for the Sleep Mode SequenceArray Initialization Initialization Mode Processing12Initialization and Configuration Array InitializationEVICTENABLE0 Initialization Mode ProcessingExternal Interface Initialization Internal Processor Register Power-Up Reset State10 Internal Processor Registers at Power-Up Reset State 14Initialization and ConfigurationInternal Processor Register Power-Up Reset State 16Initialization and Configuration Ieee 1149.1 Test Port ResetReset State Machine Ieee 1149.1 Test Port Reset11 21264/EV67 Reset State Machine State Descriptions Reset State Machine18Initialization and Configuration PLL Output Clocks Phase-Lock Loop PLL Functional DescriptionPhase-Lock Loop PLL Functional Description Differential Reference Clocks20Initialization and Configuration Power-Up/Reset ClockingError Detection and Error Handling Error Detection and Error Handling21264/EV67 Error Detection Mechanisms Data Error Correction Code Data Error Correction CodeIcache Data or Tag Parity Error Dcache Tag Parity ErrorLoad Instruction Dcache Data Single-Bit Correctable ECC ErrorDcache Data Single-Bit Correctable ECC Error Store Instruction Quadword or Smaller Dcache Store Second ErrorDcache Duplicate Tag Parity Error Dcache Store Second ErrorIcache Fill from Bcache Bcache Tag Parity ErrorBcache Data Single-Bit Correctable ECC Error Bcache Tag Parity ErrorBcache Victim Read During a Dcache/Bcache Miss Bcache Victim ReadDcache Fill from Memory Memory/System Port Single-Bit Data Correctable ECC ErrorMemory/System Port Single-Bit Data Correctable ECC Error Icache Fill from MemoryBcache Data Single-Bit Correctable ECC Error on a Probe Bcache Data Single-Bit Correctable ECC Error on a Probe3summarizes the various error cases and their ramifications Double-Bit Fill ErrorsError Case Summary Double-Bit Fill Errors10Error Detection and Error Handling Error Case SummaryMchk Cstatdstreammemdbl Mchk CstatdstreambcdblMchk Cstatistreammemdbl Page Maximum Electrical Ratings Electrical CharacteristicsElectrical Data 1lists the maximum electrical ratings for the 21264/EV67Idcpower DC CharacteristicsDC Characteristics Signal TypesInput Differential Amplifier Clock Receiver Idaclk VDD IdcpowerInput DC Reference Pin Idcref Input Differential Amplifier Receiver IDACodtp Pin Type Open-Drain Driver for Test Pins OodtpPin Type Open-Drain Output Driver OOD IOZ12 Push-Pull Output Clock Driver Oppclk 11 Push-Pull Output Driver OPPAC Test Conditions AC CharacteristicsAC Characteristics TSU TDH 13 AC SpecificationsTSU1 TDH2 AC Characteristics Page Thermal Management Operating TemperatureAmbient temperature requirement Operating Temperature at Heat Sink Center Tc10-2Thermal Management Operating TemperatureΘca at Various Airflows for 21264/EV67 Heat Sink Specifications Heat Sink Specifications10-4Thermal Management Type 1 Heat SinkType 2 Heat Sink 10-6Thermal Management Type 3 Heat SinkThermal Design Considerations Thermal Design ConsiderationsPage Testability and Diagnostics Testability and DiagnosticsTest Pins Dedicated Test Port PinsSrom Load Operation SROM/Serial Diagnostic Terminal PortSROM/Serial Diagnostic Terminal Port 11-2Testability and DiagnosticsIeee 1149.1 Instructions and Opcodes Ieee 1149.1 PortIeee 1149.1 Port TestStatH Pin 11-4Testability and DiagnosticsTestStatH Pin Srom Initialization Power-Up Self-Test and InitializationPower-Up Self-Test and Initialization Built-in Self-TestSerial Instruction Cache Load Operation 11-6Testability and DiagnosticsReferences See Appendix B for a listing of the Boundary-Scan RegisterIcache Bit Fields in an Srom Line Page Alpha Instruction Set A-1 Alpha Instruction SetAlpha Instruction Summary Table A-1 Instruction Format and Opcode NotationAlpha Instruction Summary Opr 11.46 Cmove if ≥ zero Mbr Branch to subroutinePcd Trap to PALcode Opr 11.24 Cmove if = zero15.0BE Convert quadword to Gfloating 15.0AF Convert Gfloating to quadword17.010 Convert longword to quadword 15.0BC Convert quadword to Ffloating17.02B Fcmove if ≠ zero 17.02F Fcmove if zero17.02E Fcmove if ≤ zero 17.02C Fcmove if zeroMem Load Sfloating Opr 13.40 Multiply longword with integer overflow enableOpr 13.60 Multiply quadword with integer overflow enable Opr 1C.31 Pixel errorOpr 10.02 Scaled add longword by Opr 1C.36 Pack words to bytes Mfc 18.E000 Read and clearMbr 1A.2 Return from subroutine Mfc 18.C000 Read process cycle counter 18.F000 Read and setOpcodes Reserved for Compaq Reserved OpcodesReserved Opcodes Ieee Floating-Point Instructions Ieee Floating-Point Instructions VAX Floating-Point Instructions VAX Floating-Point InstructionsIndependent Floating-Point Instructions Opcode Summary Opcode SummaryFloating-point operate instruction opcodes Mem Table A-9explains the symbols used in Table A-8Mem Res Ieee floating-point instruction opcodes14Alpha Instruction Set Ieee Floating-Point ConformanceIeee Floating-Point Conformance Alpha Instruction Set A-15 Table A-11 Exceptional Input and Output Conditions16Alpha Instruction Set Cmpteq Cmptun InputCmptlt Cmptle Input Alpha Instruction Set A-17 Fbeq Fbne Fblt Fble Fbgt Fbge LDS LDT STS STT Cpys CpysnPage Boundary-Scan Register 21264/EV67 Boundary-Scan RegisterPllvdd Boundary-Scan Register21264/EV67 Boundary-Scan Register B-3 421264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B-5 621264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B-7 821264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B-9 1021264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B-11 1221264/EV67 Boundary-Scan Register Serial Icache Load Predecode Values C-1 Serial Icache Load Predecode ValuesPage PALcode Restrictions and Guidelines D-1 PALcode Restrictions and Guidelines2PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-3 4PALcode Restrictions and Guidelines Initwritemany PALcode Restrictions and Guidelines D-56PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-7 8PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-9 Restriction 7 Replay Trap, Interrupt Code Sequence, and STF10PALcode Restrictions and Guidelines Restriction 10 Duplicate IPR Mode BitsRestriction 9 PALmode Istream Address Ranges Restriction 9 PALmode Istream Address RangesRestriction 14 Hwret Restriction 11 Ibox IPR Update SynchronizationRestriction 11 Ibox IPR Update Synchronization Restriction 13 DTB Fill Flow CollisionGuideline 16 JSR-BAD VA Guideline 20 Ictlsbe Stream Buffer EnableGuideline 16 JSR-BAD VA Restriction 21 HWRET/STALL After Hwmtpr ASN0/ASN1PALcode Restrictions and Guidelines D-13 Restriction 22 HWRET/STALL After Hwmtpr IS0/IS1Restriction 22 HWRET/STALL After Hwmtpr IS0/IS1 14PALcode Restrictions and Guidelines Restriction 25 Hwmtpr Itbia After ResetGuideline 26 Conditional Branches in PALcode Restriction 24 HWRET/STALL After Hwmtpr ICFLUSH, IcflushasmPALcode Restrictions and Guidelines D-15 Guideline 29 JSR, JMP, RET, and Jsrcor in PALcodeRestriction 30 Hwmtpr and Hwmfpr to the Cbox CSR 16PALcode Restrictions and Guidelines Restriction 30 Hwmtpr and Hwmfpr to the Cbox CSRPALcode Restrictions and Guidelines D-17 Restriction 31 ICTLVA48 UpdateRestriction 32 Pctrctl Update Restriction 31 ICTLVA48 UpdateRestriction 37 Updating VACTLVA48 Guideline 35 Hwintclr UpdateRestriction 33 Hwld Physical/Lock Use Restriction 36 Updating IctlsdePALcode Restrictions and Guidelines D-19 Restriction 40 Scrubbing a Single-Bit Error20PALcode Restrictions and Guidelines Restriction 40 Scrubbing a Single-Bit ErrorPALcode Restrictions and Guidelines D-21 Restriction 42 Updating VACTL, CCCTL, or CC IPRsRestriction 43 No Trappable Instructions Along with 22PALcode Restrictions and Guidelines Restriction 47 Cache Eviction for Single-Bit Cache ErrorsPALcode Restrictions and Guidelines D-23 Restriction 47 Cache Eviction for Single-Bit Cache Errors24PALcode Restrictions and Guidelines Table E-1 Bcache Forwarding Clock Pin Groupings 21264/EV67-to-Bcache Pin InterconnectionsForwarding Clock Pin Groupings Tag Pin Usage Late-Write Non-Bursting SSRAMsLate-Write Non-Bursting SSRAMs Data Pin UsageTable E-4 Dual-Data Rate Ssram Data Pin Usage Dual-Data Rate SSRAMsDual-Data Rate SSRAMs Data and Tag Pin UsageTable E-5 Dual-Data Rate Ssram Tag Pin Usage TrstlGlossary BIU BSR Cisc CSR CmosCPI CPUDTL DMADram DTBFpga FepromFET FEUIDU GclkJfet IowbIpga ITBMips MAFMBO MBZNvram MSINaturally Aligned NmosPlcc PALPGA PLARAS PqfpProm RAMSAM RiscROM RTLSipp SdramSimm SIPUnaligned StramTTL UartVDF UnpredictableUvprom VAFWriteblock WARNumerics IndexIndex-2 Index-3 Index-4 ECC Index-6 Index-7 Index-8 Index-9 Index-10 Index-11 Index-12