Compaq EV67, 21264 Retire of Operate Instructions into R31/F31, Bsr/Jsr, 22Internal Architecture

Retire of Operate Instructions into R31/F31

Table 2–5 Minimum Retire Latencies for Instruction Classes (Continued)

Instruction Class	Retire Stage	Comments
Floating-point DIV/SQRT	11 + latency	Add latency of unit reuse for the instruction indicated in Table
		2–4.For example, latency for a single-precision fdiv would be
		11 plus 9 from Table 2–4.Latency is 11 if hardware detects that
		no exception is possible (see Section 2.4.1).
Floating-point conditional	11	Branch instruction mispredict is reported in stage 7.
branch
BSR/JSR	10	JSR instruction mispredict is reported in stage 8.

2.4.1 Floating-Point Divide/Square Root Early Retire

The floating-point divider and square root unit can detect that, for many combinations of source operand values, no exception can be generated. Instructions with these oper- ands can be retired before the result is generated. When detected, they are retired with the same latency as the FP add class. Early retirement is not possible for the following instruction/operand/architecture state conditions:

•Instruction is not a DIV or SQRT.

•SQRT source operand is negative.

•Divide operand exponent_a is 0.

•Either operand is NaN or INF.

•Divide operand exponent_b is 0.

•Trapping mode is /I (inexact).

•INE status bit is 0.

Early retirement is also not possible for divide instructions if the resulting exponent has any of the following characteristics (EXP is the result exponent):

•DIVT, DIVG: (EXP >= 3FF16) OR (EXP <= 216)

•DIVS, DIVF: (EXP >= 7F16) OR (EXP <= 38216)

2.5Retire of Operate Instructions into R31/F31

Many instructions that have R31 or F31 as their destination are retired immediately upon decode (stage 3). These instructions do not produce a result and are removed from the pipeline as well. They do not occupy a slot in the issue queues and do not occupy a functional unit. Table 2–6lists these instructions and some of their characteristics. The instruction type in Table 2–6is from Table C-6 in Appendix C of the Alpha Architecture Handbook, Version 4.

2–22Internal Architecture Alpha 21264/EV67 Hardware Reference Manual