Compaq 21264 Replay Traps, Mbox Order Traps, Memory Reference Ordering, 11 I/O Reference Ordering

Replay Traps

The 21264/EV67 maintains the default memory data instruction ordering as shown in Table 2–10(assume address X and address Y are different).

Table 2–10 Memory Reference Ordering

First Instruction in Pair Second Instruction In Pair Reference Order

Load memory to address X Load memory to address X Store memory to address X Store memory to address X Load memory to address X Load memory to address X Store memory to address X Store memory to address X

Load memory to address X	Maintained (litmus test 1)
Load memory to address Y	Not maintained
Store memory to address X	Maintained
Store memory to address Y	Maintained
Store memory to address X	Maintained
Store memory to address Y	Not maintained
Load memory to address X	Maintained
Load memory to address Y	Not maintained

The 21264/EV67 maintains the default I/O instruction ordering as shown in Table 2–11(assume address X and address Y are different).

Table 2–11 I/O Reference Ordering

First Instruction in Pair Second Instruction in Pair Reference Order

Load I/O to address X Load I/O to address X Store I/O to address X Store I/O to address X Load I/O to address X Load I/O to address X Store I/O to address X Store I/O to address X

Load I/O to address X	Maintained
Load I/O to address Y	Maintained
Store I/O to address X	Maintained
Store I/O to address Y	Maintained
Store I/O to address X	Maintained
Store I/O to address Y	Not maintained
Load I/O to address X	Maintained
Load I/O to address Y	Not maintained

2.11 Replay Traps

There are some situations in which a load or store instruction cannot be executed due to a condition that occurs after that instruction issues from the IQ or FQ. The instruction is aborted (along with all newer instructions) and restarted from the fetch stage of the pipeline. This mechanism is called a replay trap.

2.11.1 Mbox Order Traps

Load and store instructions may be issued from the IQ in a different order than they were fetched from the Icache, while the architecture dictates that Dstream memory transactions to the same physical bytes must be completed in order. Usually, the Mbox manages the memory reference stream by itself to achieve architecturally correct behavior, but the two cases in which the Mbox uses replay traps to manage the memory stream are load-loadand store-loadorder traps.

Alpha 21264/EV67 Hardware Reference Manual Internal Architecture 2–31