Compaq 21264, EV67 specifications Pin Signal Names and Initialization State, Pll

Power-Up Reset Flow and the Reset_L and DCOK_H Pins

Table 7–3summarizes the pins and the suggested/required initialization state. Most of this information is supplied by placing (switch-selectable or hardwired) weak pull-ups or pull-downs on the IRQ_H pins. The IRQ_H pins are sampled on the rising edge of DCOK_H, during which time the 21264/EV67 is in reset and is not generating any sys- tem activity. During normal operation, the IRQ_H pins supply interrupt requests to the 21264/EV67.

It is possible to disable the 21264/EV67 PLL and source GCLK directly from ClkIn_x. This mode is selected via PllBypass_H. The 21264/EV67 still produces a divided- down clock on EV6Clk_x; this output clock, which tracks GCLK, can be used in a feedback loop to generate a locked input clock via an external PLL. The input clock can be locked against a slower speed system reference clock.

Table 7–3 Pin Signal Names and Initialization State

Signal Name	Sample Time	Function	Value
PllBypass_H	Continuous input	Select ClkIn_x onto GCLK instead of internal	0	Bypass1
		PLL.	1	Use PLL
ClkFwdRst_H	Sampling method	—	—
	according to
	IRQ_H[4]
Reset_L	Continuous input	—	—
IRQ_H[5]	Rising edge of	Select 1:1 FrameClk mode.	0	Sample with
	DCOK_H	Internal FrameClk can be generated two ways:		FrameClk_H
		1 By sampling FrameClk_H. Used if	1	Use a copy of
				EV6Clk_H
		FrameClk_H is slower than ClkIn_H.
		2 As a direct copy of EV6Clk_H. Used if
		FrameClk_H is the same frequency as
		ClkIn_H or is DC.
IRQ_H[4]	Rising edge of	Select method of sampling ClkFwdRst_H to	0	Sample with Exter-
	DCOK_H	produce internal ClkFwdRst — either with		nal FrameClk_x
		external or internal copy of FrameClk_x.	1	Sample with Inter-
				nal Frameclk

IRQ_H[3:0] Rising edge of	Select Ydiv divisor value. This is the divide-
DCOK_H	down factor between GCLK and EV6Clk_x.
	When the PLL is in use and the 21264/EV67 is
	ramped-up to full speed, the VCO adjusts in
	order to phase-align (and rate-match) EV6Clk_x
	to ClkIn_x. When the PLL is not in use, and
	ClkIn_x is bypassed onto GCLK, EV6Clk_x is
	slower than ClkIn_x by the divisor Ydiv.

IRQ_H[3:0] Divisor

0011	3
0100	4
0101	5
0110	6
0111	7
0000	8
1000	9
1001	10
1010	11
1011	12
1100	13
1101	14
1110	15
1111	16

Alpha 21264/EV67 Hardware Reference Manual Initialization and Configuration 7–5