3 21264/EV67-to-System Commands | Compaq specification

System Port

Table 4–8 Program Values for Data-Sample/Drive CSRs (Continued)

CBOX CSR	Description

SYS_DDM_RD_RISE_EN[0]	Enables the sampling of incoming data on the rising edge of the incoming
	forwarded clock. (Always asserted)
SYS_DDMF_ENABLE	Enables the falling edge of the system forwarded clock. (Always asserted)
SYS_DDMR_ENABLE	Enables the rising edge of the system forwarded clock. (Always asserted)

Table 4–9lists the program values for CSR SYS_FRAME_LD_VECTOR[4:0] that set the ratio between the forwarded clocks and the frame clock.

Table 4–9 Forwarded Clocks and Frame Clock Ratio

Clock Ratio	Transfer Mode	Value1
1:1	All	00
2:1	3.0X, 3.5X, 8.0X	1E
2:1	1.5X, 2.0X, 2.5X 4.0X, 5.0X, 6.0X 7.0X	1F
4:1	8X	15
4:1	1.5X, 4.0X, 5.0X, 6.0X, 7.0X	0B
4:1	3.0X, 3.5X	14
4:1	2.0X, 2.5X	0A

1These are hexadecimal values.

4.7.321264/EV67-to-System Commands

This section describes the 21264/EV67-to-system commands format and operation. The command, address, ID, and mask bits are transmitted in four consecutive cycles on SysAddOut_L[14:0]. The 21264/EV67 sends the command information in one of the two following modes as selected by the Cbox CSR bit.

•Bank interleave on cache block boundary mode—SYSBUS_FORMAT[0] = 0

•Page hit mode—SYSBUS_FORMAT[0] = 1

The physical address (PA) bits arrangements for the two modes is shown in Tables 4–10and 4–11.The purpose of the two modes is to give the system the PA bits that allow it to select the memory bank and drive the RAS address as soon as possible.

4.7.3.1 Bank Interleave on Cache Block Boundary Mode

Table 4–10shows the command format for the bank interleave on cache block bound- ary mode of operation (21264/EV67-to-system).

Table 4–10 Bank Interleave on Cache Block Boundary Mode of Operation

		SysAddOut_L[14:2]		SysAddOut_L[1]	SysAddOut_L[0]

Cycle 1	M1	Command[4:0]	PA[34:28]	PA[36]	PA[38]

Alpha 21264/EV67 Hardware Reference Manual

Cache and External Interfaces 4–19

Image 107

Compaq specifications 3 21264/EV67-to-System Commands, Forwarded Clocks and Frame Clock Ratio

Contents

DS-0028A-TE Revision/Update InformationAlpha 21264A Microprocessor Hardware Reference Manual Alpha 21264/EV67 Hardware Reference Manual Table of Contents Cache and External Interfaces Hardware Interface Internal Processor Registers Privileged Architecture Library Code Mffpcr Mtfpcr Initialization and Configuration Thermal Management Error Detection and Error HandlingTestability and Diagnostics Electrical Data 21264/EV67 Boundary-Scan Register Alpha Instruction Set Glossary Index 21264/EV67-to-Bcache Pin Interconnections Figures Xii Tables Xiv VDD Idcpower Page Audience ContentPreface Documentation Included by Reference Abbreviations Terminology and ConventionsFor example Aligned and Unaligned W1CW1S Addresses External Signal NamesData Units Do Not Care Undefined Do not care. a capital X represents any valid value Page Introduction IntroductionArchitecture Floating-Point Data Types ArchitectureAddressing Integer Data Types 21264/EV67 Microprocessor Features 21264/EV67 Microprocessor Features 21264/EV67 Microprocessor Features Internal Architecture Internal Architecture21264/EV67 Microarchitecture Virtual Program Counter Logic Instruction Fetch, Issue, and Retire Unit21264/EV67 Microarchitecture Branch Predictor 21264/EV67 Block Diagram Global Predictor Local Predictor Instruction-Stream Translation Buffer Choice Predictor Register Rename Maps Integer Issue QueueInstruction Fetch Logic Hwret Floating-Point Issue Queue Retire Logic Integer Execution UnitException and Interrupt Logic Integer Execution Unit-Clusters 0 PERR, MINxxx, MAXxxx, UNPKxx, PKxx 10Internal Architecture Floating-Point Execution Unit 21264/EV67 contains two onchip primary-level caches External Cache and System Interface UnitOnchip Caches 12Internal Architecture Memory Reference UnitData Cache Miss address file MAF Dstream translation buffer DTB Pipeline OrganizationPipeline Organization Srom Interface 14Internal Architecture Stage 0 Instruction FetchStage 1 Instruction Slot Stage 2 Map Stage 3 Issue Ebox and Fbox pipelines begin execution Instruction Issue RulesInstruction Issue Rules Pipeline Aborts Instruction Name, Pipeline, and Types Instruction Issue Rules Instruction Group Definitions Instruction Group Definitions and Pipeline Unit Ebox SlottingFTOIS, Ftoit ITOFS, ITOFF, Itoft U U L E L U E E L L E U 20Internal Architecture Instruction Issue Rules Instruction LatenciesInstruction Class Latency in Cycles Hwmfpr Minimum Retire Latencies for Instruction Classes Instruction Retire RulesInstruction Retire Rules BSR/JSR Retire of Operate Instructions into R31/F31Retire of Operate Instructions into R31/F31 Floating-Point Divide/Square Root Early Retire Instructions Retired Without Execution Load Instructions to R31 and F31Load Instructions to R31 and F31 Prefetch with Modify Intent LDS Instruction 24Internal Architecture Special Cases of Alpha Instruction ExecutionPrefetch with the LDxL / STxC Instruction Sequence Load Hit Speculation Pipeline Timing for Integer Load Instructions Special Cases of Alpha Instruction Execution 26Internal Architecture Floating-Point Store InstructionsCmov Instruction Memory Address Space Load Instructions Memory and I/O Address Space InstructionsMemory and I/O Address Space Instructions 28Internal Architecture 2 I/O Address Space Load InstructionsRules for I/O Address Space Load Instruction Data Merging Rules for I/O Address Space Store Instruction Data Merging 4 I/O Address Space Store Instructions8shows some of the following rules MAF Merging Rules MAF Memory Address Space Merging RulesInstruction Ordering MAF Memory Address Space Merging Rules 10 Memory Reference Ordering Replay TrapsReplay Traps Mbox Order Traps Memory Barrier MB/WMB/TB Fill Flow 12 I/O Write Buffer and the WMB InstructionWrite Buffer and the WMB Instruction Other Mbox Replay Traps MB Instruction Processing 34Internal Architecture WMB Instruction ProcessingTB Fill Flow 12 TB Fill Flow Example Sequence 13 TB Fill Flow Example Sequence Floating-point control register Fpcr is shown in Figure Performance Measurement Support-Performance CountersFloating-Point Control Register Performance Measurement Support-Performance Counters Floating-Point Control Register Implver Amask and Implver Instruction ValuesAmask and Implver Instruction Values Amask Design Examples Design Examples 40Internal Architecture 13 Typical Multiprocessor Configuration Hardware Interface 21264/EV67 Microprocessor Logic SymbolHardware Interface 21264/EV67 Microprocessor Logic Symbol 21264/EV67 Microprocessor Logic Symbol 21264/EV67 Signal Descriptions 21264/EV67 Signal Names and Functions21264/EV67 Signal Names and Functions Signal Pin Types Definitions Dcokh Pllvdd TestStatH 21264/EV67 Signal Descriptions by Function SysVref Domain SysAddInL140 Pin Assignments Pin List Sorted by Signal NamePin Assignments AC1 Pllvdd 10Hardware Interface AA5 12Hardware Interface Pin List Sorted by PGA Location SysDataL28 14Hardware Interface BcDataH70 SysDataL5 16Hardware Interface Ground and Power VSS and VDD Pin List Mechanical Specifications Mechanical Specifications 18Hardware Interface 21264/EV67 Packaging21264/EV67 Packaging 21264/EV67 Bottom View Pin Up Page Cache and External Interfaces Cache and External InterfacesIntroduction to the External Interfaces Introduction to the External Interfaces 21264/EV67 System and Bcache Interfaces System Interface Second-Level Cache Bcache Interface Commands and AddressesPhysical Address Considerations Physical Address Considerations MB/WMB ECB I/O Physical Address Considerations System Duplicate Tag Stores Bcache Interface SignalsBcache Structure Bcache Structure Cache Coherency Basics Victim Data BufferCache Coherency Victim Data Buffer 21264/EV67-Supported Cache Block States Cache CoherencyCache Block States 2lists the cache block states supported by the 21264/EV67 10Cache and External Interfaces System Responses to 21264/EV67 CommandsCache Block State Transitions Cache Block State Transitions Cache Coherency Using SysDc Commands 12Cache and External Interfaces Dcache States and Duplicate Tags 14Cache and External Interfaces Lock MechanismLock Mechanism Liveness and Fairness Internal Eviction of LDxL Blocks 16Cache and External Interfaces System PortSystem Port System Port Pins System Port Pins 18Cache and External Interfaces System Port Programming the System Interface ClocksProgramming Values for System Interface Clocks Program Values for Data-Sample/Drive CSRs Forwarded Clocks and Frame Clock Ratio 3 21264/EV67-to-System CommandsBank Interleave on Cache Block Boundary Mode 12describes the field definitions for Tables 4-10and Hit Mode11 Page Hit Mode of Operation 12 21264/EV67-to-System Command Fields Definitions 13 Maximum Physical Address for Short Bus Format 4 21264/EV67-to-System Commands Descriptions14describes the 21264/EV67-to-system commands 14 21264/EV67-to-System Commands Descriptions 22Cache and External Interfaces 15 Programming INVALTODIRTYENABLE10 24Cache and External Interfaces ProbeResponse Commands Command40 =16 Programming SETDIRTYENABLE20 17 21264/EV67 ProbeResponse Command 18 ProbeResponse Fields Descriptions SysAck and 21264/EV67-to-System Commands Flow Control18describes the ProbeResponse command fields RVB RPB System-to-21264/EV67 CommandsProbe Commands Four Cycles 19 System-to-21264/EV67 Probe Commands 21 Data Movement Selection by Probe43 20 System-to-21264/EV67 Probe Commands Fields Descriptions21 lists the data movement selected by Probe43 22lists the next cache block state selected by Probe20 28Cache and External Interfaces Data Transfer Commands Two Cycles23 Data Transfer Command Format 24 SysDc40 Field Description 24describes the SysDc40 field 30Cache and External Interfaces Data Movement In and Out of the 21264/EV678.1 21264/EV67 Clock Basics Fast Data Mode 32Cache and External Interfaces 25 Sysclk Cycles Between SysAddOut and SysData Fast Data Disable Mode 26shows four example configurations and shows their use26 Cbox CSR SYSDCDELAY40 Examples 34Cache and External Interfaces 27 Four Timing ExamplesSysDataInValidL and SysDataOutValidL SysDataInValidL SysFillValidL SysDataOutValidL 36Cache and External Interfaces Data Wrapping28 Data Wrapping Rules 30 Wrap Interleave Order 30defines the interleaved scheme for the wrap order29 System Wrap and Deliver Data 38Cache and External Interfaces Nonexistent Memory Processing31defines the wrap order for double-pumped data transfers 31 Wrap Order for Double-Pumped Data Transfers 21264/EV67 Command NXM Address System/21264/EV67 Response 40Cache and External Interfaces 10.1 21264/EV67 Commands and System ProbesOrdering of System Port Transactions System Port Bcache Port Bcache Port 35 Range of Maximum Bcache Clock Ratios Bcache Port Pins36 Bcache Port Pins 44Cache and External Interfaces Bcache Clocking Setting the Period of the Cache Clock 37 BCCPUCLKDELAY10 Values38 BCCLKDELAY10 Values 46Cache and External Interfaces 39 Program Values to Set the Cache Clock Period Single-Data Bcache Data Read and Tag Read Transactions Bcache Transactions41 Data-Sample/Drive Cbox CSRs 48Cache and External Interfaces Bcache Data Write Transactions Dual-data mode, bcfrm is twice the ratio When the ratio is even, bcfrm is equal to the ratioWhen the ratio is odd, bcfrm is twice the ratio For example, in single-data mode 50Cache and External Interfaces BcAddH234 Pin DescriptionsRelationship Between Write-to-Read Bcwrrdbubbles and wrrd Relationship Between Read-to-Write Bcrdwrbubbles and rdwr 44lists the combination of control pin assertion for BcDataInClkH and BcTagInClkH 46 Control Pin Assertion for Ramtype C47 Control Pin Assertion for Ramtype D 54Cache and External Interfaces InterruptsInterrupts Bcache Banking Disabling the Bcache for Debugging Internal Processor Registers Internal Processor Registers Mbox IPRs Cycle Counter Control Register Ccctl Ebox IPRsEbox IPRs Cycle Counter Register CC Cycle Counter Control Register Fields Description Virtual Address Register VAVirtual Address Control Register Vactl 2describes the Ccctl register fields VAFORM32 Virtual Address Format Register Vaform3describes the virtual address control register fields Virtual Address Control Register Fields Description ITB PTE Array Write Register Itbpte Ibox IPRsIbox IPRs ITB Tag Array Write Register Itbtag ITB Invalidate Single Register Itbis ITB Invalidate All Process ASM=0 Register ItbiapITB Invalidate All Register Itbia ProfileMe PC Fields Description Ibox IPRs ProfileMe PC Register PmpcException Address Register Excaddr 4describes the ProfileMe PC register fields 13shows Ivaform when ICTLVA48 equals 0 ICTLVAFORM32 equals Interrupt Enable and Current Processor Mode Register Iercm 10Internal Processor Registers Software Interrupt Request Register SirrIercm Register Fields Description Software Interrupt Request Register Fields Description Interrupt Summary Register Isum6describes the software interrupt request register fields 12Internal Processor Registers Hardware Interrupt Clear Register Hwintclr7describes the interrupt summary register fields Interrupt Summary Register Fields Description Mchkd W1C Exception Summary Register Excsum8describes the hardware interrupt clear register fields Hardware Interrupt Clear Register Fields Description 14Internal Processor Registers 9describes the exception summary register fieldsException Summary Register Fields Description 10 PAL Base Register Fields Description PAL Base Register PalbaseIbox Control Register Ictl 10describes the PAL base register fields 16Internal Processor Registers 11describes the Ibox control register fields11 Ibox Control Register Fields Description PCT1EN SingleissuehMchken STWAIT64K 18Internal Processor Registers Ibox Status Register IstatSpce TRP 12describes the Ibox status register fields12 Ibox Status Register Fields Description MIS 20Internal Processor Registers Clear Virtual-to-Physical Map Register Clrmap Sleep Mode Register SleepIbox IPRs Icache Flush Register Icflush Icache Flush ASM Register Icflushasm 22Internal Processor Registers 14describes the process context register fields14 Process Context Register Fields Description Ppce Performance Counter Control Register PctrctlFPE 24Internal Processor Registers 15describes the performance counter control register fields15 Performance Counter Control Register Fields Description 16 Performance Counter Control Register Input Select Fields Mbox IPRsMbox IPRs DTB Tag Array Write Registers 0 and 1 DTBTAG0, DTBTAG1 26Internal Processor Registers DTB Alternate Processor Mode Register Dtbaltmode Dstream TB Invalidate Single Registers 0 and 1 DTBIS0,1 17 DTB Alternate Processor Mode Register Fields DescriptionDstream TB Invalidate All Process ASM=0 Register Dtbiap Dstream TB Invalidate All Register Dtbia 28Internal Processor Registers Memory Management Status Register Mmstat18describes the memory management status register fields 18 Memory Management Status Register Fields Description ACV Mbox Control Register MctlFor 19 Mbox Control Register Fields Description Erences to superpages result in access violationsDcache Control Register Dcctl 19describes the Mbox control register fields 20 Dcache Control Register Fields Description Dcache Status Register Dcstat20describes the Dcache control register fields 21 Dcache Status Register Fields Description Cbox CSRs and IPRsCbox CSRs and IPRs 21describes the Dcache status register fields 22 describes the Cbox data register fields Cbox CSRs and IPRs Cbox Data Register CdataCbox Shift Register Cshft Cbox Writeonce Chain Description 34Internal Processor Registers 24 Cbox Writeonce Chain Order Skewedfillmode Mboxbcprbstall BCLATDATAPATTERN031 BCLATTAGPATTERN023 36Internal Processor Registers SYSCLKDELAY10 38Internal Processor Registers Cbox Writemany Chain Description 25 Cbox Writemany Chain Order 25describes the Cbox Writemany chain order from LSB to MSB 40Internal Processor Registers Setdirtyenable = Bcbankenable = 26 Cbox Read IPR Fields Description Cbox CSRs and IPRs Cbox Read Register IPR DescriptionPage Privileged Architecture Library Code Privileged Architecture Library CodePALcode Description PALmode Environment PALmode Environment Hwld Instruction Required PALcode Function CodesOpcodes Reserved for PALcode Required PALcode Function Codes Hwld Instruction Fields Descriptions Opcodes Reserved for PALcodeHwst Instruction 3describes the Hwld instruction fields Hwst Instruction Fields Descriptions Hwret Instruction4describes the Hwst instruction fields Hint Hwmfpr and Hwmtpr Instructions5describes the Hwret instruction fields Hwret Instruction Fields Descriptions Hwmfpr and Hwmtpr Instructions Fields Descriptions Internal Processor Register Access MechanismsInternal Processor Register Access Mechanisms 6describes the Hwmfpr and Hwmtpr instructions fields Hardware Structure of Explicitly Written IPRs Paired Instruction Fetch Order IPR Access Ordering 10Privileged Architecture Library Code PALcode Emulation of the Fpcr PALshadow Registers PALcode Entry Points PALcode Exception Entry Locations PALcode Exception Entry Points 14Privileged Architecture Library Code Translation Buffer TB Fill FlowsTranslation Buffer TB Fill Flows DTB Fill Wr PTE LD-PTE, write TB Wr DataTb miss 16Privileged Architecture Library Code ITB Fill Performance Counter Support Performance Counter Support IPRs Used for Performance Counter Support General PrecautionsAggregate Mode Programming Guidelines Aggregate Mode Precautions SL1 10 Aggregate Mode Returned IPR ContentsOperation Pctrctl SL0 This input counts Mbox replay traps ProfileMe Mode Programming Guidelines11shows the counter modes that are used with Aggregate mode 12 Cmov Decomposed 22Privileged Architecture Library Code 13 ProfileMe Mode Returned IPR Contents Inum retire delay cycles ProfileMe Counting Mode Description Cycle counting 24Privileged Architecture Library Code 14shows the counter modes that are used with ProfileMe modeCounter Modes for ProfileMe Mode 14 ProfileMe Mode Pctrctl Input Select Fields Initialization and Configuration Initialization and ConfigurationPower-Up Reset Flow and the ResetL and Dcokh Pins 21264/EV67 Reset State Machine Major Operations Constraints Power-Up Reset Flow and the ResetL and Dcokh Pins Signal Pin Reset State Power Sequencing and Reset State for Signal Pins Pllvdd Clock Forwarding and System Clock Ratio Configuration PLL Pin Signal Names and Initialization State BiST and Srom Load and the TestStatH Pin PLL Ramp Up Power-Up Flow Signals and Their Constraints Clock Forward Reset and System Interface Initialization Effect on IPRs After Fault Reset Fault Reset FlowFault Reset Flow Energy Star Certification and Sleep Mode Flow Energy Star Certification and Sleep Mode Flow 10Initialization and Configuration Effect on IPRs After Transition Through Sleep Mode Effect on IPRs After Warm Reset Warm Reset FlowWarm Reset Flow Signals and Constraints for the Sleep Mode Sequence Array Initialization Initialization Mode Processing12Initialization and Configuration Array Initialization EVICTENABLE0 Initialization Mode Processing External Interface Initialization Internal Processor Register Power-Up Reset State10 Internal Processor Registers at Power-Up Reset State 14Initialization and Configuration Internal Processor Register Power-Up Reset State 16Initialization and Configuration Ieee 1149.1 Test Port ResetReset State Machine Ieee 1149.1 Test Port Reset 11 21264/EV67 Reset State Machine State Descriptions Reset State Machine 18Initialization and Configuration PLL Output Clocks Phase-Lock Loop PLL Functional DescriptionPhase-Lock Loop PLL Functional Description Differential Reference Clocks 20Initialization and Configuration Power-Up/Reset Clocking Error Detection and Error Handling Error Detection and Error Handling21264/EV67 Error Detection Mechanisms Data Error Correction Code Data Error Correction CodeIcache Data or Tag Parity Error Dcache Tag Parity Error Load Instruction Dcache Data Single-Bit Correctable ECC ErrorDcache Data Single-Bit Correctable ECC Error Store Instruction Quadword or Smaller Dcache Store Second ErrorDcache Duplicate Tag Parity Error Dcache Store Second Error Icache Fill from Bcache Bcache Tag Parity ErrorBcache Data Single-Bit Correctable ECC Error Bcache Tag Parity Error Bcache Victim Read During a Dcache/Bcache Miss Bcache Victim Read Dcache Fill from Memory Memory/System Port Single-Bit Data Correctable ECC ErrorMemory/System Port Single-Bit Data Correctable ECC Error Icache Fill from Memory Bcache Data Single-Bit Correctable ECC Error on a Probe Bcache Data Single-Bit Correctable ECC Error on a Probe 3summarizes the various error cases and their ramifications Double-Bit Fill ErrorsError Case Summary Double-Bit Fill Errors 10Error Detection and Error Handling Error Case Summary Mchk Cstatdstreammemdbl Mchk CstatdstreambcdblMchk Cstatistreammemdbl Page Maximum Electrical Ratings Electrical CharacteristicsElectrical Data 1lists the maximum electrical ratings for the 21264/EV67 Idcpower DC CharacteristicsDC Characteristics Signal Types Input Differential Amplifier Clock Receiver Idaclk VDD IdcpowerInput DC Reference Pin Idcref Input Differential Amplifier Receiver IDA Codtp Pin Type Open-Drain Driver for Test Pins OodtpPin Type Open-Drain Output Driver OOD IOZ 12 Push-Pull Output Clock Driver Oppclk 11 Push-Pull Output Driver OPP AC Test Conditions AC CharacteristicsAC Characteristics TSU TDH 13 AC Specifications TSU1 TDH2 AC Characteristics Page Thermal Management Operating TemperatureAmbient temperature requirement Operating Temperature at Heat Sink Center Tc 10-2Thermal Management Operating TemperatureΘca at Various Airflows for 21264/EV67 Heat Sink Specifications Heat Sink Specifications 10-4Thermal Management Type 1 Heat Sink Type 2 Heat Sink 10-6Thermal Management Type 3 Heat Sink Thermal Design Considerations Thermal Design ConsiderationsPage Testability and Diagnostics Testability and DiagnosticsTest Pins Dedicated Test Port Pins Srom Load Operation SROM/Serial Diagnostic Terminal PortSROM/Serial Diagnostic Terminal Port 11-2Testability and Diagnostics Ieee 1149.1 Instructions and Opcodes Ieee 1149.1 PortIeee 1149.1 Port TestStatH Pin 11-4Testability and DiagnosticsTestStatH Pin Srom Initialization Power-Up Self-Test and InitializationPower-Up Self-Test and Initialization Built-in Self-Test Serial Instruction Cache Load Operation 11-6Testability and Diagnostics References See Appendix B for a listing of the Boundary-Scan RegisterIcache Bit Fields in an Srom Line Page Alpha Instruction Set A-1 Alpha Instruction SetAlpha Instruction Summary Table A-1 Instruction Format and Opcode Notation Alpha Instruction Summary Opr 11.46 Cmove if ≥ zero Mbr Branch to subroutinePcd Trap to PALcode Opr 11.24 Cmove if = zero 15.0BE Convert quadword to Gfloating 15.0AF Convert Gfloating to quadword17.010 Convert longword to quadword 15.0BC Convert quadword to Ffloating 17.02B Fcmove if ≠ zero 17.02F Fcmove if zero17.02E Fcmove if ≤ zero 17.02C Fcmove if zero Mem Load Sfloating Opr 13.40 Multiply longword with integer overflow enableOpr 13.60 Multiply quadword with integer overflow enable Opr 1C.31 Pixel error Opr 10.02 Scaled add longword by Opr 1C.36 Pack words to bytes Mfc 18.E000 Read and clearMbr 1A.2 Return from subroutine Mfc 18.C000 Read process cycle counter 18.F000 Read and set Opcodes Reserved for Compaq Reserved OpcodesReserved Opcodes Ieee Floating-Point Instructions Ieee Floating-Point Instructions VAX Floating-Point Instructions VAX Floating-Point InstructionsIndependent Floating-Point Instructions Opcode Summary Opcode Summary Floating-point operate instruction opcodes Mem Table A-9explains the symbols used in Table A-8Mem Res Ieee floating-point instruction opcodes 14Alpha Instruction Set Ieee Floating-Point ConformanceIeee Floating-Point Conformance Alpha Instruction Set A-15 Table A-11 Exceptional Input and Output Conditions 16Alpha Instruction Set Cmpteq Cmptun InputCmptlt Cmptle Input Alpha Instruction Set A-17 Fbeq Fbne Fblt Fble Fbgt Fbge LDS LDT STS STT Cpys CpysnPage Boundary-Scan Register 21264/EV67 Boundary-Scan Register Pllvdd Boundary-Scan Register 21264/EV67 Boundary-Scan Register B-3 421264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B-5 621264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B-7 821264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B-9 1021264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B-11 1221264/EV67 Boundary-Scan Register Serial Icache Load Predecode Values C-1 Serial Icache Load Predecode ValuesPage PALcode Restrictions and Guidelines D-1 PALcode Restrictions and Guidelines 2PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-3 4PALcode Restrictions and Guidelines Initwritemany PALcode Restrictions and Guidelines D-5 6PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-7 8PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-9 Restriction 7 Replay Trap, Interrupt Code Sequence, and STF 10PALcode Restrictions and Guidelines Restriction 10 Duplicate IPR Mode BitsRestriction 9 PALmode Istream Address Ranges Restriction 9 PALmode Istream Address Ranges Restriction 14 Hwret Restriction 11 Ibox IPR Update SynchronizationRestriction 11 Ibox IPR Update Synchronization Restriction 13 DTB Fill Flow Collision Guideline 16 JSR-BAD VA Guideline 20 Ictlsbe Stream Buffer EnableGuideline 16 JSR-BAD VA Restriction 21 HWRET/STALL After Hwmtpr ASN0/ASN1 PALcode Restrictions and Guidelines D-13 Restriction 22 HWRET/STALL After Hwmtpr IS0/IS1Restriction 22 HWRET/STALL After Hwmtpr IS0/IS1 14PALcode Restrictions and Guidelines Restriction 25 Hwmtpr Itbia After ResetGuideline 26 Conditional Branches in PALcode Restriction 24 HWRET/STALL After Hwmtpr ICFLUSH, Icflushasm PALcode Restrictions and Guidelines D-15 Guideline 29 JSR, JMP, RET, and Jsrcor in PALcodeRestriction 30 Hwmtpr and Hwmfpr to the Cbox CSR 16PALcode Restrictions and Guidelines Restriction 30 Hwmtpr and Hwmfpr to the Cbox CSR PALcode Restrictions and Guidelines D-17 Restriction 31 ICTLVA48 UpdateRestriction 32 Pctrctl Update Restriction 31 ICTLVA48 Update Restriction 37 Updating VACTLVA48 Guideline 35 Hwintclr UpdateRestriction 33 Hwld Physical/Lock Use Restriction 36 Updating Ictlsde PALcode Restrictions and Guidelines D-19 Restriction 40 Scrubbing a Single-Bit Error 20PALcode Restrictions and Guidelines Restriction 40 Scrubbing a Single-Bit Error PALcode Restrictions and Guidelines D-21 Restriction 42 Updating VACTL, CCCTL, or CC IPRsRestriction 43 No Trappable Instructions Along with 22PALcode Restrictions and Guidelines Restriction 47 Cache Eviction for Single-Bit Cache Errors PALcode Restrictions and Guidelines D-23 Restriction 47 Cache Eviction for Single-Bit Cache Errors 24PALcode Restrictions and Guidelines Table E-1 Bcache Forwarding Clock Pin Groupings 21264/EV67-to-Bcache Pin InterconnectionsForwarding Clock Pin Groupings Tag Pin Usage Late-Write Non-Bursting SSRAMsLate-Write Non-Bursting SSRAMs Data Pin Usage Table E-4 Dual-Data Rate Ssram Data Pin Usage Dual-Data Rate SSRAMsDual-Data Rate SSRAMs Data and Tag Pin Usage Table E-5 Dual-Data Rate Ssram Tag Pin Usage Trstl Glossary BIU BSR Cisc CSR CmosCPI CPU DTL DMADram DTB Fpga FepromFET FEU IDU Gclk Jfet IowbIpga ITB Mips MAFMBO MBZ Nvram MSINaturally Aligned Nmos Plcc PALPGA PLA RAS PqfpProm RAM SAM RiscROM RTL Sipp SdramSimm SIP Unaligned StramTTL Uart VDF UnpredictableUvprom VAF Writeblock WAR Numerics Index Index-2 Index-3 Index-4 ECC Index-6 Index-7 Index-8 Index-9 Index-10 Index-11 Index-12