Compaq EV67, 21264 Ebox Slotting, FTOIS, Ftoit, ITOFS, ITOFF, Itoft, 18Internal Architecture

Instruction Issue Rules

Table 2–2 Instruction Name, Pipeline, and Types (Continued)

Class
Name	Pipeline	Instruction Type
ftoi	FST0, FST1, L0, L1	FTOIS, FTOIT
itof	L0, L1	ITOFS, ITOFF, ITOFT
mx_fpcr	FM	Instructions that move data from the floating-point
		control register

2.3.2 Ebox Slotting

Instructions that are issued from the IQ, and could execute in either upper or lower Ebox subclusters, are slotted to one pair or the other during the pipeline mapping stage based on the instruction mixture in the fetch line. The codes that are used in Table 2–3are as follows:

•U—The instruction only executes in an upper subcluster.

•L—The instruction only executes in a lower subcluster.

•E—The instruction could execute in either an upper or lower subcluster.

Table 2–3defines the slotting rules. The table field Instruction Class 3, 2, 1 and 0 iden- tifies each instruction’s location in the fetch line by the value of bits [3:2] in its PC.

Table 2–3 Instruction Group Definitions and Pipeline Unit

Instruction Class	Slotting	Instruction Class	Slotting
3 2 1 0	3 2 1 0	3 2 1 0	3 2 1 0

E E E E E E E L E E E U E E L E E E L L E E L U E E U E E E U L E E U U E L E E E L E L E L E U E L L E E L L L E L L U E L U E E L U L

U L U L U L U L U L L U U L L U U U L L U L L U U L U L U L U L L L U U U L U L U L U L U L L U U L L U U L L L U L L U U L U L U L U L

L L L L L L L U L L U E L L U L L L U U L U E E L U E L L U E U L U L E L U L L L U L U L U U E L U U L L U U U U E E E U E E L U E E U

L L L L L L L U L L U U L L U L L L U U L U L U L U U L L U L U L U L U L U L L L U L U L U U L L U U L L U U U U L U L U L U L U L L U

2–18Internal Architecture Alpha 21264/EV67 Hardware Reference Manual