Compaq 21264, EV67 specifications Figures

Figures

2–1	21264/EV67 Block Diagram	2–3
2–2	Branch Predictor	2–4
2–3	Local Predictor	2–4
2–4	Global Predictor	2–5
2–5	Choice Predictor	2–5
2–6	Integer Execution Unit—Clusters 0 and 1	2–9
2–7	Floating-Point Execution Units	2–10
2–8	Pipeline Organization	2–14
2–9	Pipeline Timing for Integer Load Instructions	2–25
2–10	Pipeline Timing for Floating-Point Load Instructions	2–26
2–11	Floating-Point Control Register	2–36
2–12	Typical Uniprocessor Configuration	2–39
2–13	Typical Multiprocessor Configuration	2–40
3–1	21264/EV67 Microprocessor Logic Symbol	3–2
3–2	Package Dimensions	3–17
3–3	21264/EV67 Top View (Pin Down)	3–18
3–4	21264/EV67 Bottom View (Pin Up)	3–19
4–1	21264/EV67 System and Bcache Interfaces	4–3
4–2	21264/EV67 Bcache Interface Signals	4–7
4–3	Cache Subset Hierarchy	4–9
4–4	System Interface Signals	4–17
4–5	Fast Transfer Timing Example	4–32
4–6	SysFillValid_L Timing	4–36
5–1	Cycle Counter Register	5–3
5–2	Cycle Counter Control Register	5–3
5–3	Virtual Address Register	5–4
5–4	Virtual Address Control Register	5–4
5–5	Virtual Address Format Register (VA_48 = 0, VA_FORM_32 = 0)	5–5
5–6	Virtual Address Format Register (VA_48 = 1, VA_FORM_32 = 0)	5–6
5–7	Virtual Address Format Register (VA_48 = 0, VA_FORM_32 = 1)	5–6
5–8	ITB Tag Array Write Register	5–6
5–9	ITB PTE Array Write Register	5–7
5–10	ITB Invalidate Single Register	5–7
5–11	ProfileMe PC Register	5–8
5–12	Exception Address Register	5–8
5–13	Instruction Virtual Address Format Register (VA_48 = 0, VA_FORM_32 = 0)	5–9
5–14	Instruction Virtual Address Format Register (VA_48 = 1, VA_FORM_32 = 0)	5–9
5–15	Instruction Virtual Address Format Register (VA_48 = 0, VA_FORM_32 = 1)	5–9
5–16	Interrupt Enable and Current Processor Mode Register	5–10
5–17	Software Interrupt Request Register	5–11
5–18	Interrupt Summary Register	5–11
5–19	Hardware Interrupt Clear Register	5–12
5–20	Exception Summary Register	5–14
5–21	PAL Base Register	5–15
5–22	Ibox Control Register	5–16
5–23	Ibox Status Register	5–19
5–24	Process Context Register	5–22
5–25	Performance Counter Control Register	5–23
5–26	DTB Tag Array Write Registers 0 and 1	5–25
5–27	DTB PTE Array Write Registers 0 and 1	5–26
5–28	DTB Alternate Processor Mode Register	5–26
5–29	Dstream Translation Buffer Invalidate Single Registers	5–27
5–30	Dstream Translation Buffer Address Space Number Registers 0 and 1	5–28
5–31	Memory Management Status Register	5–28
5–32	Mbox Control Register	5–29
5–33	Dcache Control Register	5–31

Alpha 21264/EV67 Hardware Reference Manual xi