Compaq EV67, 21264 specifications Privileged Architecture Library Code

5.1.3	Virtual Address Register – VA	5–4
5.1.4	Virtual Address Control Register – VA_CTL	5–4
5.1.5	Virtual Address Format Register – VA_FORM	5–5
5.2	Ibox IPRs	5–6
5.2.1	ITB Tag Array Write Register – ITB_TAG	5–6
5.2.2	ITB PTE Array Write Register – ITB_PTE	5–6
5.2.3	ITB Invalidate All Process (ASM=0) Register – ITB_IAP	5–7
5.2.4	ITB Invalidate All Register – ITB_IA	5–7
5.2.5	ITB Invalidate Single Register – ITB_IS	5–7
5.2.6	ProfileMe PC Register – PMPC	5–8
5.2.7	Exception Address Register – EXC_ADDR	5–8
5.2.8	Instruction Virtual Address Format Register — IVA_FORM	5–9
5.2.9	Interrupt Enable and Current Processor Mode Register – IER_CM	5–9
5.2.10	Software Interrupt Request Register – SIRR	5–10
5.2.11	Interrupt Summary Register – ISUM	5–11
5.2.12	Hardware Interrupt Clear Register – HW_INT_CLR	5–12
5.2.13	Exception Summary Register – EXC_SUM	5–13
5.2.14	PAL Base Register – PAL_BASE	5–15
5.2.15	Ibox Control Register – I_CTL	5–15
5.2.16	Ibox Status Register – I_STAT	5–18
5.2.17	Icache Flush Register – IC_FLUSH	5–21
5.2.18	Icache Flush ASM Register – IC_FLUSH_ASM	5–21
5.2.19	Clear Virtual-to-Physical Map Register – CLR_MAP	5–21
5.2.20	Sleep Mode Register – SLEEP	5–21
5.2.21	Process Context Register – PCTX	5–21
5.2.22	Performance Counter Control Register – PCTR_CTL	5–23
5.3	Mbox IPRs	5–25
5.3.1	DTB Tag Array Write Registers 0 and 1 – DTB_TAG0, DTB_TAG1	5–25
5.3.2	DTB PTE Array Write Registers 0 and 1 – DTB_PTE0, DTB_PTE1	5–26
5.3.3	DTB Alternate Processor Mode Register – DTB_ALTMODE	5–26
5.3.4	Dstream TB Invalidate All Process (ASM=0) Register – DTB_IAP	5–27
5.3.5	Dstream TB Invalidate All Register – DTB_IA	5–27
5.3.6	Dstream TB Invalidate Single Registers 0 and 1 – DTB_IS0,1	5–27
5.3.7	Dstream TB Address Space Number Registers 0 and 1 – DTB_ASN0,1	5–28
5.3.8	Memory Management Status Register – MM_STAT	5–28
5.3.9	Mbox Control Register – M_CTL	5–29
5.3.10	Dcache Control Register – DC_CTL	5–30
5.3.11	Dcache Status Register – DC_STAT	5–31
5.4	Cbox CSRs and IPRs	5–32
5.4.1	Cbox Data Register – C_DATA	5–33
5.4.2	Cbox Shift Register – C_SHFT	5–33
5.4.3	Cbox WRITE_ONCE Chain Description	5–33
5.4.4	Cbox WRITE_MANY Chain Description	5–38
5.4.5	Cbox Read Register (IPR) Description	5–41

6 Privileged Architecture Library Code

6.1	PALcode Description	6–1
6.2	PALmode Environment	6–2
6.3	Required PALcode Function Codes	6–3
6.4	Opcodes Reserved for PALcode	6–3
6.4.1	HW_LD Instruction	6–3
6.4.2	HW_ST Instruction	6–4
6.4.3	HW_RET Instruction	6–5
6.4.4	HW_MFPR and HW_MTPR Instructions	6–6
6.5	Internal Processor Register Access Mechanisms	6–7
6.5.1	IPR Scoreboard Bits	6–8

vi Alpha 21264/EV67 Hardware Reference Manual