Phase-Lock Loop (PLL) Functional Description

Table 7–12shows the allowable ClkIn_x frequencies for a given operating frequency of the 21264/EV67 and the Ydiv divider. For example, to set the 21264/EV67 GCLK frequency to 500 MHz with a ClkIn_x frequency of 166.7 MHz, the system must select a Ydiv divider of 3 by placing the value 00112 on pins IRQ_H[3:0].

Table 7–12 Differential Reference Clock Frequencies in Full-Speed Lock

GCLK

 

Reference Clock Frequency (MHz) for Ydiv Dividers1

 

 

 

Period (ns)

Frequency (MHz)

32

4

5

6

7

8

 

9

10

11

2.5

400

133.3

100

80

 

 

2.4

416.7

138.9

104.2

83.3

 

 

2.3

434.8

144.9

108.7

87.0

 

 

2.2

454.5

151.2

113.6

90.9

 

 

2.1

476.2

158.7

119.0

95.2

 

 

2.0

500

166.7

125.0

100

83.3

 

 

1.9

526.3

175.4

131.6

105.3

87.7

 

 

1.8

555.6

185.2

138.9

111.1

92.6

 

 

1.7

588.2

196.1

147.1

117.6

98.0

84.0

 

 

1.6

625

156.3

125.0

104.2

89.3

 

 

1.5

666.7

166.7

133.3

111.1

95.2

83.3

 

 

1.4

714.3

178.6

142.9

119.1

102.0

89.3

 

 

1.3

769.2

192.3

153.8

128.2

109.9

96.2

 

85.5

 

1.2

833.3

166.7 138.9

119.0

104.2

92.6

83.3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1Dividers 11 through 16 are out of range for the 21264/EV67 and reserved for future use. Valid refer- ence clock (ClkIn_x) frequencies for the 21264/EV67 are specified in the range from 80 to 200. Divider values that are out of that range are displayed as a dash “—”.

2Dividers of 1 and 2 are to be used only in a PLL test mode.

7.11.2.4Power-Up/Reset Clocking

During the power-up/reset sequence, when not in PLL bypass mode, there may be a period of time when ClkIn_x is not yet running, but there is a voltage on PLL_VDD. The signal DCOK_H is deasserted until power is good throughout the system. The 10% to 90% rise time of DCOK_H should be less than 2 ns. The deasserted state of DCOK_H and the presence of PLL_VDD causes the PLL to generate a global clock that is distributed throughout the 21264/EV67 with a frequency range of 1 MHz to 500 MHz. The presence of the global clock during this period avoids permanent damage to the 21264/EV67.

7–20Initialization and Configuration

Alpha 21264/EV67 Hardware Reference Manual

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Compaq EV67, 21264 specifications Power-Up/Reset Clocking, 20Initialization and Configuration