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Compaq EV67, 21264 specifications Typical Multiprocessor Configuration, 40Internal Architecture

Models: 21264 EV67

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Design Examples

Figure 2–13 Typical Multiprocessor Configuration

Cache

21264

21272 Core

Logic Chipset

Control

Chip

Data Slice

Chips

Host PCI		Host PCI
Bridge Chip		Bridge Chip

DRAM

Arrays

Address

Data

DRAM

Arrays

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64-bit PCI Bus

FM-05574-EV67

2–40Internal Architecture

Alpha 21264/EV67 Hardware Reference Manual

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Compaq EV67, 21264 specifications Typical Multiprocessor Configuration, 40Internal Architecture

Contents

Revision/Update Information Alpha 21264A MicroprocessorHardware Reference Manual DS-0028A-TEAlpha 21264/EV67 Hardware Reference Manual Table of Contents Hardware Interface Cache and External InterfacesInternal Processor Registers Privileged Architecture Library Code Initialization and Configuration Mffpcr MtfpcrError Detection and Error Handling Testability and DiagnosticsElectrical Data Thermal ManagementAlpha Instruction Set 21264/EV67 Boundary-Scan Register21264/EV67-to-Bcache Pin Interconnections Glossary IndexFigures Xii Tables Xiv VDD Idcpower Page Audience ContentPreface Documentation Included by Reference Abbreviations Terminology and ConventionsFor example W1C W1SAddresses Aligned and UnalignedSignal Names Data UnitsDo Not Care ExternalUndefined Do not care. a capital X represents any valid value Page Introduction IntroductionArchitecture Architecture AddressingInteger Data Types Floating-Point Data Types21264/EV67 Microprocessor Features 21264/EV67 Microprocessor Features21264/EV67 Microprocessor Features Internal Architecture Internal Architecture21264/EV67 Microarchitecture Virtual Program Counter Logic Instruction Fetch, Issue, and Retire Unit21264/EV67 Microarchitecture 21264/EV67 Block Diagram Branch PredictorLocal Predictor Global PredictorChoice Predictor Instruction-Stream Translation BufferRegister Rename Maps Integer Issue QueueInstruction Fetch Logic Floating-Point Issue Queue HwretRetire Logic Integer Execution UnitException and Interrupt Logic PERR, MINxxx, MAXxxx, UNPKxx, PKxx Integer Execution Unit-Clusters 0Floating-Point Execution Unit 10Internal Architecture21264/EV67 contains two onchip primary-level caches External Cache and System Interface UnitOnchip Caches 12Internal Architecture Memory Reference UnitData Cache Pipeline Organization Pipeline OrganizationSrom Interface Miss address file MAF Dstream translation buffer DTB14Internal Architecture Stage 0 Instruction FetchStage 1 Instruction Slot Stage 3 Issue Stage 2 MapInstruction Issue Rules Instruction Issue RulesPipeline Aborts Ebox and Fbox pipelines begin executionInstruction Issue Rules Instruction Group Definitions Instruction Name, Pipeline, and TypesEbox Slotting FTOIS, FtoitITOFS, ITOFF, Itoft Instruction Group Definitions and Pipeline UnitU U L E L U E E L L E U Instruction Issue Rules Instruction Latencies Instruction Class Latency in CyclesHwmfpr 20Internal ArchitectureMinimum Retire Latencies for Instruction Classes Instruction Retire RulesInstruction Retire Rules Retire of Operate Instructions into R31/F31 Retire of Operate Instructions into R31/F31Floating-Point Divide/Square Root Early Retire BSR/JSRLoad Instructions to R31 and F31 Load Instructions to R31 and F31Prefetch with Modify Intent LDS Instruction Instructions Retired Without ExecutionSpecial Cases of Alpha Instruction Execution Prefetch with the LDxL / STxC Instruction SequenceLoad Hit Speculation 24Internal ArchitectureSpecial Cases of Alpha Instruction Execution Pipeline Timing for Integer Load Instructions26Internal Architecture Floating-Point Store InstructionsCmov Instruction Memory Address Space Load Instructions Memory and I/O Address Space InstructionsMemory and I/O Address Space Instructions 28Internal Architecture 2 I/O Address Space Load InstructionsRules for I/O Address Space Load Instruction Data Merging Rules for I/O Address Space Store Instruction Data Merging 4 I/O Address Space Store Instructions8shows some of the following rules MAF Memory Address Space Merging Rules Instruction OrderingMAF Memory Address Space Merging Rules MAF Merging RulesReplay Traps Replay TrapsMbox Order Traps 10 Memory Reference Ordering12 I/O Write Buffer and the WMB Instruction Write Buffer and the WMB InstructionOther Mbox Replay Traps Memory Barrier MB/WMB/TB Fill FlowMB Instruction Processing WMB Instruction Processing TB Fill Flow12 TB Fill Flow Example Sequence 34Internal Architecture13 TB Fill Flow Example Sequence Performance Measurement Support-Performance Counters Floating-Point Control RegisterPerformance Measurement Support-Performance Counters Floating-point control register Fpcr is shown in FigureFloating-Point Control Register Amask and Implver Instruction Values Amask and Implver Instruction ValuesAmask ImplverDesign Examples Design Examples13 Typical Multiprocessor Configuration 40Internal ArchitectureHardware Interface 21264/EV67 Microprocessor Logic SymbolHardware Interface 21264/EV67 Microprocessor Logic Symbol 21264/EV67 Microprocessor Logic Symbol21264/EV67 Signal Names and Functions 21264/EV67 Signal Names and FunctionsSignal Pin Types Definitions 21264/EV67 Signal DescriptionsDcokh Pllvdd 21264/EV67 Signal Descriptions by Function TestStatHSysVref Domain SysAddInL140 Pin Assignments Pin List Sorted by Signal NamePin Assignments AC1 10Hardware Interface PllvddAA5 Pin List Sorted by PGA Location 12Hardware InterfaceSysDataL28 14Hardware Interface BcDataH70 SysDataL5 Ground and Power VSS and VDD Pin List 16Hardware InterfaceMechanical Specifications Mechanical Specifications18Hardware Interface 21264/EV67 Packaging21264/EV67 Packaging 21264/EV67 Bottom View Pin Up Page Cache and External Interfaces Cache and External InterfacesIntroduction to the External Interfaces Introduction to the External Interfaces System Interface 21264/EV67 System and Bcache InterfacesCommands and Addresses Physical Address ConsiderationsPhysical Address Considerations Second-Level Cache Bcache InterfaceECB I/O MB/WMBPhysical Address Considerations Bcache Interface Signals Bcache StructureBcache Structure System Duplicate Tag StoresVictim Data Buffer Cache CoherencyVictim Data Buffer Cache Coherency BasicsCache Coherency Cache Block States2lists the cache block states supported by the 21264/EV67 21264/EV67-Supported Cache Block StatesSystem Responses to 21264/EV67 Commands Cache Block State TransitionsCache Block State Transitions 10Cache and External InterfacesCache Coherency Using SysDc Commands 12Cache and External Interfaces Dcache States and Duplicate Tags 14Cache and External Interfaces Lock MechanismLock Mechanism Internal Eviction of LDxL Blocks Liveness and Fairness16Cache and External Interfaces System PortSystem Port System Port Pins System Port PinsSystem Port Programming the System Interface Clocks Programming Values for System Interface ClocksProgram Values for Data-Sample/Drive CSRs 18Cache and External InterfacesForwarded Clocks and Frame Clock Ratio 3 21264/EV67-to-System CommandsBank Interleave on Cache Block Boundary Mode Hit Mode 11 Page Hit Mode of Operation12 21264/EV67-to-System Command Fields Definitions 12describes the field definitions for Tables 4-10and4 21264/EV67-to-System Commands Descriptions 14describes the 21264/EV67-to-system commands14 21264/EV67-to-System Commands Descriptions 13 Maximum Physical Address for Short Bus Format22Cache and External Interfaces 15 Programming INVALTODIRTYENABLE10 ProbeResponse Commands Command40 = 16 Programming SETDIRTYENABLE2017 21264/EV67 ProbeResponse Command 24Cache and External Interfaces18 ProbeResponse Fields Descriptions SysAck and 21264/EV67-to-System Commands Flow Control18describes the ProbeResponse command fields System-to-21264/EV67 Commands Probe Commands Four Cycles19 System-to-21264/EV67 Probe Commands RVB RPB20 System-to-21264/EV67 Probe Commands Fields Descriptions 21 lists the data movement selected by Probe4322lists the next cache block state selected by Probe20 21 Data Movement Selection by Probe4328Cache and External Interfaces Data Transfer Commands Two Cycles23 Data Transfer Command Format 24describes the SysDc40 field 24 SysDc40 Field Description30Cache and External Interfaces Data Movement In and Out of the 21264/EV678.1 21264/EV67 Clock Basics Fast Data Mode 25 Sysclk Cycles Between SysAddOut and SysData 32Cache and External InterfacesFast Data Disable Mode 26shows four example configurations and shows their use26 Cbox CSR SYSDCDELAY40 Examples 27 Four Timing Examples SysDataInValidL and SysDataOutValidLSysDataInValidL 34Cache and External InterfacesSysDataOutValidL SysFillValidL36Cache and External Interfaces Data Wrapping28 Data Wrapping Rules 30 Wrap Interleave Order 30defines the interleaved scheme for the wrap order29 System Wrap and Deliver Data Nonexistent Memory Processing 31defines the wrap order for double-pumped data transfers31 Wrap Order for Double-Pumped Data Transfers 38Cache and External Interfaces21264/EV67 Command NXM Address System/21264/EV67 Response 40Cache and External Interfaces 10.1 21264/EV67 Commands and System ProbesOrdering of System Port Transactions System Port Bcache Port Bcache Port35 Range of Maximum Bcache Clock Ratios Bcache Port Pins36 Bcache Port Pins Bcache Clocking 44Cache and External InterfacesSetting the Period of the Cache Clock 37 BCCPUCLKDELAY10 Values38 BCCLKDELAY10 Values 39 Program Values to Set the Cache Clock Period Single-Data 46Cache and External InterfacesBcache Data Read and Tag Read Transactions Bcache Transactions41 Data-Sample/Drive Cbox CSRs Bcache Data Write Transactions 48Cache and External InterfacesWhen the ratio is even, bcfrm is equal to the ratio When the ratio is odd, bcfrm is twice the ratioFor example, in single-data mode Dual-data mode, bcfrm is twice the ratio50Cache and External Interfaces Pin Descriptions Relationship Between Write-to-Read Bcwrrdbubbles and wrrdRelationship Between Read-to-Write Bcrdwrbubbles and rdwr BcAddH23444lists the combination of control pin assertion for BcDataInClkH and BcTagInClkH 46 Control Pin Assertion for Ramtype C47 Control Pin Assertion for Ramtype D Interrupts Interrupts Bcache BankingDisabling the Bcache for Debugging 54Cache and External InterfacesInternal Processor Registers Internal Processor RegistersMbox IPRs Ebox IPRs Ebox IPRsCycle Counter Register CC Cycle Counter Control Register CcctlVirtual Address Register VA Virtual Address Control Register Vactl2describes the Ccctl register fields Cycle Counter Control Register Fields DescriptionVirtual Address Format Register Vaform 3describes the virtual address control register fieldsVirtual Address Control Register Fields Description VAFORM32Ibox IPRs Ibox IPRsITB Tag Array Write Register Itbtag ITB PTE Array Write Register ItbpteITB Invalidate Single Register Itbis ITB Invalidate All Process ASM=0 Register ItbiapITB Invalidate All Register Itbia Ibox IPRs ProfileMe PC Register Pmpc Exception Address Register Excaddr4describes the ProfileMe PC register fields ProfileMe PC Fields DescriptionInterrupt Enable and Current Processor Mode Register Iercm 13shows Ivaform when ICTLVA48 equals 0 ICTLVAFORM32 equals10Internal Processor Registers Software Interrupt Request Register SirrIercm Register Fields Description Software Interrupt Request Register Fields Description Interrupt Summary Register Isum6describes the software interrupt request register fields Hardware Interrupt Clear Register Hwintclr 7describes the interrupt summary register fieldsInterrupt Summary Register Fields Description 12Internal Processor RegistersException Summary Register Excsum 8describes the hardware interrupt clear register fieldsHardware Interrupt Clear Register Fields Description Mchkd W1C14Internal Processor Registers 9describes the exception summary register fieldsException Summary Register Fields Description PAL Base Register Palbase Ibox Control Register Ictl10describes the PAL base register fields 10 PAL Base Register Fields Description16Internal Processor Registers 11describes the Ibox control register fields11 Ibox Control Register Fields Description Singleissueh MchkenSTWAIT64K PCT1EN18Internal Processor Registers Ibox Status Register IstatSpce 12describes the Ibox status register fields 12 Ibox Status Register Fields DescriptionMIS TRP20Internal Processor Registers Sleep Mode Register Sleep Ibox IPRs Icache Flush Register IcflushIcache Flush ASM Register Icflushasm Clear Virtual-to-Physical Map Register Clrmap22Internal Processor Registers 14describes the process context register fields14 Process Context Register Fields Description Ppce Performance Counter Control Register PctrctlFPE 24Internal Processor Registers 15describes the performance counter control register fields15 Performance Counter Control Register Fields Description Mbox IPRs Mbox IPRsDTB Tag Array Write Registers 0 and 1 DTBTAG0, DTBTAG1 16 Performance Counter Control Register Input Select FieldsDTB Alternate Processor Mode Register Dtbaltmode 26Internal Processor Registers17 DTB Alternate Processor Mode Register Fields Description Dstream TB Invalidate All Process ASM=0 Register DtbiapDstream TB Invalidate All Register Dtbia Dstream TB Invalidate Single Registers 0 and 1 DTBIS0,1Memory Management Status Register Mmstat 18describes the memory management status register fields18 Memory Management Status Register Fields Description 28Internal Processor RegistersACV Mbox Control Register MctlFor Erences to superpages result in access violations Dcache Control Register Dcctl19describes the Mbox control register fields 19 Mbox Control Register Fields Description20 Dcache Control Register Fields Description Dcache Status Register Dcstat20describes the Dcache control register fields Cbox CSRs and IPRs Cbox CSRs and IPRs21describes the Dcache status register fields 21 Dcache Status Register Fields DescriptionCbox CSRs and IPRs Cbox Data Register Cdata Cbox Shift Register CshftCbox Writeonce Chain Description 22 describes the Cbox data register fields24 Cbox Writeonce Chain Order 34Internal Processor RegistersMboxbcprbstall BCLATDATAPATTERN031 BCLATTAGPATTERN023 Skewedfillmode36Internal Processor Registers SYSCLKDELAY10 Cbox Writemany Chain Description 38Internal Processor Registers25describes the Cbox Writemany chain order from LSB to MSB 25 Cbox Writemany Chain OrderSetdirtyenable = Bcbankenable = 40Internal Processor RegistersCbox CSRs and IPRs Cbox Read Register IPR Description 26 Cbox Read IPR Fields DescriptionPage Privileged Architecture Library Code Privileged Architecture Library CodePALcode Description PALmode Environment PALmode EnvironmentRequired PALcode Function Codes Opcodes Reserved for PALcodeRequired PALcode Function Codes Hwld InstructionOpcodes Reserved for PALcode Hwst Instruction3describes the Hwld instruction fields Hwld Instruction Fields DescriptionsHwst Instruction Fields Descriptions Hwret Instruction4describes the Hwst instruction fields Hwmfpr and Hwmtpr Instructions 5describes the Hwret instruction fieldsHwret Instruction Fields Descriptions HintInternal Processor Register Access Mechanisms Internal Processor Register Access Mechanisms6describes the Hwmfpr and Hwmtpr instructions fields Hwmfpr and Hwmtpr Instructions Fields DescriptionsHardware Structure of Explicitly Written IPRs IPR Access Ordering Paired Instruction Fetch Order10Privileged Architecture Library Code PALshadow Registers PALcode Emulation of the FpcrPALcode Entry Points PALcode Exception Entry Points PALcode Exception Entry LocationsTranslation Buffer TB Fill Flows Translation Buffer TB Fill FlowsDTB Fill 14Privileged Architecture Library CodeWr PTE LD-PTE, write TB Wr DataTb miss ITB Fill 16Privileged Architecture Library CodePerformance Counter Support Performance Counter SupportGeneral Precautions Aggregate Mode Programming GuidelinesAggregate Mode Precautions IPRs Used for Performance Counter Support10 Aggregate Mode Returned IPR Contents OperationPctrctl SL0 SL1This input counts Mbox replay traps ProfileMe Mode Programming Guidelines11shows the counter modes that are used with Aggregate mode 12 Cmov Decomposed 13 ProfileMe Mode Returned IPR Contents 22Privileged Architecture Library CodeProfileMe Counting Mode Description Cycle counting Inum retire delay cycles14shows the counter modes that are used with ProfileMe mode Counter Modes for ProfileMe Mode14 ProfileMe Mode Pctrctl Input Select Fields 24Privileged Architecture Library CodeInitialization and Configuration Power-Up Reset Flow and the ResetL and Dcokh Pins21264/EV67 Reset State Machine Major Operations Initialization and ConfigurationPower-Up Reset Flow and the ResetL and Dcokh Pins ConstraintsPower Sequencing and Reset State for Signal Pins Signal Pin Reset StateClock Forwarding and System Clock Ratio Configuration PllvddPin Signal Names and Initialization State PLLPLL Ramp Up BiST and Srom Load and the TestStatH PinClock Forward Reset and System Interface Initialization Power-Up Flow Signals and Their ConstraintsEffect on IPRs After Fault Reset Fault Reset FlowFault Reset Flow Energy Star Certification and Sleep Mode Flow Energy Star Certification and Sleep Mode FlowEffect on IPRs After Transition Through Sleep Mode 10Initialization and ConfigurationWarm Reset Flow Warm Reset FlowSignals and Constraints for the Sleep Mode Sequence Effect on IPRs After Warm ResetInitialization Mode Processing 12Initialization and ConfigurationArray Initialization Array InitializationInitialization Mode Processing EVICTENABLE0Internal Processor Register Power-Up Reset State 10 Internal Processor Registers at Power-Up Reset State14Initialization and Configuration External Interface InitializationInternal Processor Register Power-Up Reset State Ieee 1149.1 Test Port Reset Reset State MachineIeee 1149.1 Test Port Reset 16Initialization and ConfigurationReset State Machine 11 21264/EV67 Reset State Machine State Descriptions18Initialization and Configuration Phase-Lock Loop PLL Functional Description Phase-Lock Loop PLL Functional DescriptionDifferential Reference Clocks PLL Output ClocksPower-Up/Reset Clocking 20Initialization and ConfigurationError Detection and Error Handling Error Detection and Error Handling21264/EV67 Error Detection Mechanisms Data Error Correction Code Icache Data or Tag Parity ErrorDcache Tag Parity Error Data Error Correction CodeLoad Instruction Dcache Data Single-Bit Correctable ECC ErrorDcache Data Single-Bit Correctable ECC Error Dcache Store Second Error Dcache Duplicate Tag Parity ErrorDcache Store Second Error Store Instruction Quadword or SmallerBcache Tag Parity Error Bcache Data Single-Bit Correctable ECC ErrorBcache Tag Parity Error Icache Fill from BcacheBcache Victim Read Bcache Victim Read During a Dcache/Bcache MissMemory/System Port Single-Bit Data Correctable ECC Error Memory/System Port Single-Bit Data Correctable ECC ErrorIcache Fill from Memory Dcache Fill from MemoryBcache Data Single-Bit Correctable ECC Error on a Probe Bcache Data Single-Bit Correctable ECC Error on a ProbeDouble-Bit Fill Errors Error Case SummaryDouble-Bit Fill Errors 3summarizes the various error cases and their ramificationsError Case Summary 10Error Detection and Error HandlingMchk Cstatdstreammemdbl Mchk CstatdstreambcdblMchk Cstatistreammemdbl Page Electrical Characteristics Electrical Data1lists the maximum electrical ratings for the 21264/EV67 Maximum Electrical RatingsDC Characteristics DC CharacteristicsSignal Types IdcpowerVDD Idcpower Input DC Reference Pin IdcrefInput Differential Amplifier Receiver IDA Input Differential Amplifier Clock Receiver IdaclkPin Type Open-Drain Driver for Test Pins Oodtp Pin Type Open-Drain Output Driver OODIOZ Codtp11 Push-Pull Output Driver OPP 12 Push-Pull Output Clock Driver OppclkAC Test Conditions AC CharacteristicsAC Characteristics 13 AC Specifications TSU TDHTSU1 TDH2 AC Characteristics Page Operating Temperature Ambient temperature requirementOperating Temperature at Heat Sink Center Tc Thermal Management10-2Thermal Management Operating TemperatureΘca at Various Airflows for 21264/EV67 Heat Sink Specifications Heat Sink SpecificationsType 1 Heat Sink 10-4Thermal ManagementType 2 Heat Sink Type 3 Heat Sink 10-6Thermal ManagementThermal Design Considerations Thermal Design ConsiderationsPage Testability and Diagnostics Test PinsDedicated Test Port Pins Testability and DiagnosticsSROM/Serial Diagnostic Terminal Port SROM/Serial Diagnostic Terminal Port11-2Testability and Diagnostics Srom Load OperationIeee 1149.1 Instructions and Opcodes Ieee 1149.1 PortIeee 1149.1 Port TestStatH Pin 11-4Testability and DiagnosticsTestStatH Pin Power-Up Self-Test and Initialization Power-Up Self-Test and InitializationBuilt-in Self-Test Srom Initialization11-6Testability and Diagnostics Serial Instruction Cache Load OperationReferences See Appendix B for a listing of the Boundary-Scan RegisterIcache Bit Fields in an Srom Line Page Alpha Instruction Set Alpha Instruction SummaryTable A-1 Instruction Format and Opcode Notation Alpha Instruction Set A-1Alpha Instruction Summary Mbr Branch to subroutine Pcd Trap to PALcodeOpr 11.24 Cmove if = zero Opr 11.46 Cmove if ≥ zero15.0AF Convert Gfloating to quadword 17.010 Convert longword to quadword15.0BC Convert quadword to Ffloating 15.0BE Convert quadword to Gfloating17.02F Fcmove if zero 17.02E Fcmove if ≤ zero17.02C Fcmove if zero 17.02B Fcmove if ≠ zeroOpr 13.40 Multiply longword with integer overflow enable Opr 13.60 Multiply quadword with integer overflow enableOpr 1C.31 Pixel error Mem Load SfloatingOpr 1C.36 Pack words to bytes Mfc 18.E000 Read and clear Mbr 1A.2 Return from subroutineMfc 18.C000 Read process cycle counter 18.F000 Read and set Opr 10.02 Scaled add longword byOpcodes Reserved for Compaq Reserved OpcodesReserved Opcodes Ieee Floating-Point Instructions Ieee Floating-Point Instructions VAX Floating-Point Instructions VAX Floating-Point InstructionsIndependent Floating-Point Instructions Opcode Summary Opcode SummaryMem Table A-9explains the symbols used in Table A-8 Mem ResIeee floating-point instruction opcodes Floating-point operate instruction opcodes14Alpha Instruction Set Ieee Floating-Point ConformanceIeee Floating-Point Conformance Table A-11 Exceptional Input and Output Conditions Alpha Instruction Set A-1516Alpha Instruction Set Cmpteq Cmptun InputCmptlt Cmptle Input Fbeq Fbne Fblt Fble Fbgt Fbge LDS LDT STS STT Cpys Cpysn Alpha Instruction Set A-17Page 21264/EV67 Boundary-Scan Register Boundary-Scan RegisterBoundary-Scan Register Pllvdd21264/EV67 Boundary-Scan Register B-3 421264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B-5 621264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B-7 821264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B-9 1021264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B-11 1221264/EV67 Boundary-Scan Register Serial Icache Load Predecode Values Serial Icache Load Predecode Values C-1Page PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-12PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-3 4PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-5 Initwritemany6PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-7 8PALcode Restrictions and Guidelines Restriction 7 Replay Trap, Interrupt Code Sequence, and STF PALcode Restrictions and Guidelines D-9Restriction 10 Duplicate IPR Mode Bits Restriction 9 PALmode Istream Address RangesRestriction 9 PALmode Istream Address Ranges 10PALcode Restrictions and GuidelinesRestriction 11 Ibox IPR Update Synchronization Restriction 11 Ibox IPR Update SynchronizationRestriction 13 DTB Fill Flow Collision Restriction 14 HwretGuideline 20 Ictlsbe Stream Buffer Enable Guideline 16 JSR-BAD VARestriction 21 HWRET/STALL After Hwmtpr ASN0/ASN1 Guideline 16 JSR-BAD VAPALcode Restrictions and Guidelines D-13 Restriction 22 HWRET/STALL After Hwmtpr IS0/IS1Restriction 22 HWRET/STALL After Hwmtpr IS0/IS1 Restriction 25 Hwmtpr Itbia After Reset Guideline 26 Conditional Branches in PALcodeRestriction 24 HWRET/STALL After Hwmtpr ICFLUSH, Icflushasm 14PALcode Restrictions and GuidelinesPALcode Restrictions and Guidelines D-15 Guideline 29 JSR, JMP, RET, and Jsrcor in PALcodeRestriction 30 Hwmtpr and Hwmfpr to the Cbox CSR Restriction 30 Hwmtpr and Hwmfpr to the Cbox CSR 16PALcode Restrictions and GuidelinesRestriction 31 ICTLVA48 Update Restriction 32 Pctrctl UpdateRestriction 31 ICTLVA48 Update PALcode Restrictions and Guidelines D-17Guideline 35 Hwintclr Update Restriction 33 Hwld Physical/Lock UseRestriction 36 Updating Ictlsde Restriction 37 Updating VACTLVA48Restriction 40 Scrubbing a Single-Bit Error PALcode Restrictions and Guidelines D-19Restriction 40 Scrubbing a Single-Bit Error 20PALcode Restrictions and GuidelinesPALcode Restrictions and Guidelines D-21 Restriction 42 Updating VACTL, CCCTL, or CC IPRsRestriction 43 No Trappable Instructions Along with Restriction 47 Cache Eviction for Single-Bit Cache Errors 22PALcode Restrictions and GuidelinesRestriction 47 Cache Eviction for Single-Bit Cache Errors PALcode Restrictions and Guidelines D-2324PALcode Restrictions and Guidelines Table E-1 Bcache Forwarding Clock Pin Groupings 21264/EV67-to-Bcache Pin InterconnectionsForwarding Clock Pin Groupings Late-Write Non-Bursting SSRAMs Late-Write Non-Bursting SSRAMsData Pin Usage Tag Pin UsageDual-Data Rate SSRAMs Dual-Data Rate SSRAMsData and Tag Pin Usage Table E-4 Dual-Data Rate Ssram Data Pin UsageTrstl Table E-5 Dual-Data Rate Ssram Tag Pin UsageGlossary BIU BSR Cisc Cmos CPICPU CSRDMA DramDTB DTLFeprom FETFEU FpgaGclk IDUIowb IpgaITB JfetMAF MBOMBZ MipsMSI Naturally AlignedNmos NvramPAL PGAPLA PlccPqfp PromRAM RASRisc ROMRTL SAMSdram SimmSIP SippStram TTLUart UnalignedUnpredictable UvpromVAF VDFWAR WriteblockIndex NumericsIndex-2 Index-3 Index-4 ECC Index-6 Index-7 Index-8 Index-9 Index-10 Index-11 Index-12