Compaq EV67 External Interface Initialization, Internal Processor Register Power-Up Reset State

External Interface Initialization

SweepMemory:

turn_on_bcache:

for 2 X bc_size

{ WH64 address }

for 2 X dcache size

{ECB address } (done)

;Write good parity/ecc to memory by

;writing a all memory locations. This is ;done by WH64 of memory addresses

;bc_enable_a	0
;bc_size_a	Actual Bcache size
;zeroblk_enable_a	3
;set_dirty_enable_a	6
;init_mode_a	0
;enable_evict_a	0
;bc_wrt_sts_a	0
;bc_bank_enable_a	0

;This loop generates legal ECC data, and ;invalidate tags which are written to the ;Bcache for all but the final 64KB of address.

;and cleans up the Dcache also.

In addition to initialization, the dynamic programming ability of the WRITE_MANY chain provides the basic tools to build various other software flows such as dynamically changing the Bcache enable/size parameters for performance testing.

7.7 External Interface Initialization

After reset, the system interface is in the default configuration dictated by the reset state of the IPR bits that select the configuration options.

The response to system interface commands and internally generated memory accesses is determined by this default configuration. System environments that are not compati- ble with the default configuration must use the SROM Icache load feature to initially load and execute a PALcode program to configure the external system interface unit IPRs as needed.

7.8 Internal Processor Register Power-Up Reset State

Many IPR bits are not initialized by reset. They are located in error-reporting registers and other IPR states. They must be initialized by initialization PALcode. Tables 7–5,7–6,and 7–8,list the effects on IPRs by fault reset, transition through sleep mode, and warm reset, respectively. Table 7–10lists the state of all internal processor registers (IPRs) immediately following power-up reset. The table also specifies which registers need to be initialized by power-up PALcode.

Table 7–10 Internal Processor Registers at Power-Up Reset State

Mnemonic	Register Name	Reset State	Comments
Ibox IPRs
ITB_TAG	ITB tag array write	X	—
ITB_PTE	ITB PTE array write	X	—

7–14Initialization and Configuration Alpha 21264/EV67 Hardware Reference Manual