Compaq 21264, EV67 7.7 External Interface Initialization, 7.8 Internal Processor Register Power-Up Reset State

7–14 Initialization and Configuration Alpha 21264/EV67 Hardware Reference Manual
External Interface Initialization
SweepMemory: ;Write good parity/ecc to memory by
; writing a all memory locations. Th is is
;done by WH64 of memory addresses
turn_on_bcache: ;bc_enable_a 0
;bc_size_a Actual Bcache size
;zeroblk_enable_a 3
;set_dirty_enable_a 6
;init_mode_a 0
;enable_evict_a 0
;bc_wrt_sts_a 0
;bc_bank_enable_a 0
for 2 X bc_size ;This loop generates legal ECC data, and
{ WH64 address } ;invalidate tags whi ch are written t o the
;Bcache for all but the final 64KB of address.
for 2 X dcache size
{ ECB address } ;and cleans up the Dc ache also.
(done)
In addition to initialization, the dynamic programming ability of the WRITE_MANY
chain provides the basic tools to build various other software flows such as d ynamically
changing the Bcache enable/size parameters for p erformance testing.
7.7 External Interface Initialization
After reset, the system interface is in the default configuration dictate d by the res et stat e
of the IPR bits that select the configuration options.
The response to system interface commands and internally generated memory acces se s
is determined by this default configuration. System environments that are not compati-
ble with the default configuration must use the SROM Icache load feature to initially
load and execute a PALcode program to configure the external system interface unit
IPRs as needed.
7.8 Internal Processor Register Power-Up Reset State
Many IPR bits are not initialized by reset. They ar e located in error-reporting registers
and other IPR states. They must be initialized by initialization PALcode. Tables 7–5,
7–6, and 7–8, list the effects on IPRs by fault reset, transition through sleep mode, and
warm reset, respectively. Table 7–10 lists the state of all internal processor registers
(IPRs) immediately following power-up reset. The table also specifies which registers
need to be initialized by power-up PALcode.
Table 7–10 Internal Processor Registers at Power-Up Reset State
Mnemonic Register Name Reset State Comments
Ibox IPRs
ITB_TAG ITB tag array write X —
ITB_PTE ITB PTE array write X —