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Compaq 21264, EV67 specifications Cbox CSRs and IPRs Cbox Read Register IPR Description

Models: 21264 EV67

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Cbox CSRs and IPRs

5.4.5 Cbox Read Register (IPR) Description

The Cbox read register is read 6 bits at a time. Table 5–26shows the ordering from LSB to MSB.

Table 5–26 Cbox Read IPR Fields Description

Name	Description

C_SYNDROME_1[7:0]

C_SYNDROME_0[7:0]

C_STAT[4:0]

If CMD is ChxToDirty, then C_SYNDROME_1 is X; otherwise, is syndrome for upper QW in OW of victim that was scrubbed.

If CMD is ChxToDirty, then C_SYNDROME_0 is X; otherwise, is syndrome for lower QW in OW of victim that was scrubbed.

Bits	Error Status
0 0 0 0 0	Either no error, or error on a speculative load, or a Bcache vic-
	tim read due to a Dcache/Bcache miss

0 0 0 0 1	BC_PERR (Bcache tag parity error)
0 0 0 1 0	DC_PERR (duplicate tag parity error)
0 0 0 1 1	DSTREAM_MEM_ERR
0 0 1 0 0	DSTREAM_BC_ERR
0 0 1 0 1	DSTREAM_DC_ERR
0 0 1 1 X	PROBE_BC_ERR
0 1 0 0 0	Reserved
0 1 0 0 1	Reserved
0 1 0 1 0	Reserved
0 1 0 1 1	ISTREAM_MEM_ERR
0 1 1 0 0	ISTREAM_BC_ERR
0 1 1 0 1	Reserved
0 1 1 1 X	Reserved
1 0 0 1 1	DSTREAM_MEM_DBL1
1 0 1 0 0	DSTREAM_BC_DBL1
1 1 0 1 1	ISTREAM_MEM_DBL1
1 1 1 0 0	ISTREAM_BC_DBL1

	1 Error status as specified only when Cbox WRITE_ONCE chain bit
	SKEWED_ FILL_MODE[0] is clear; otherwise, error status is
	generic DOUBLE_BIT_ERROR (1XXXX).
C_STS[3:0]	If C_STAT equals xxx_MEM_ERR or xxx_BC_ERR, then C_STS contains the
	status of the block as follows; otherwise, the value of C_STS is X:
	Bit Value	Status of Block
	7:4	Reserved
	3	Parity
	2	Valid
	1	Dirty
	0	Shared
C_ADDR[6:42]	Address of last reported ECC or parity error. If C_STAT value is
	DSTREAM_DC_ERR, only bits 6:19 are valid. If C_STAT value is
	DOUBLE_BIT_ERROR and SKEWED_FILL_MODE[0] is set, then C_ADDR
	is X.

Alpha 21264/EV67 Hardware Reference Manual

Internal Processor Registers 5–41

Image 183

Compaq 21264, EV67 specifications Cbox CSRs and IPRs Cbox Read Register IPR Description, Cbox Read IPR Fields Description

Contents

DS-0028A-TE Revision/Update InformationAlpha 21264A Microprocessor Hardware Reference ManualAlpha 21264/EV67 Hardware Reference Manual Table of Contents Cache and External Interfaces Hardware InterfaceInternal Processor Registers Privileged Architecture Library Code Mffpcr Mtfpcr Initialization and ConfigurationThermal Management Error Detection and Error HandlingTestability and Diagnostics Electrical Data21264/EV67 Boundary-Scan Register Alpha Instruction SetGlossary Index 21264/EV67-to-Bcache Pin InterconnectionsFigures Xii Tables Xiv VDD Idcpower Page Content PrefaceAudience Documentation Included by Reference Terminology and Conventions For exampleAbbreviations Aligned and Unaligned W1CW1S AddressesExternal Signal NamesData Units Do Not CareUndefined Do not care. a capital X represents any valid value Page Introduction ArchitectureIntroduction Floating-Point Data Types ArchitectureAddressing Integer Data Types21264/EV67 Microprocessor Features 21264/EV67 Microprocessor Features21264/EV67 Microprocessor Features Internal Architecture 21264/EV67 MicroarchitectureInternal Architecture Instruction Fetch, Issue, and Retire Unit 21264/EV67 MicroarchitectureVirtual Program Counter Logic Branch Predictor 21264/EV67 Block DiagramGlobal Predictor Local PredictorInstruction-Stream Translation Buffer Choice PredictorInteger Issue Queue Instruction Fetch LogicRegister Rename Maps Hwret Floating-Point Issue QueueInteger Execution Unit Exception and Interrupt LogicRetire Logic Integer Execution Unit-Clusters 0 PERR, MINxxx, MAXxxx, UNPKxx, PKxx10Internal Architecture Floating-Point Execution UnitExternal Cache and System Interface Unit Onchip Caches21264/EV67 contains two onchip primary-level caches Memory Reference Unit Data Cache12Internal Architecture Miss address file MAF Dstream translation buffer DTB Pipeline OrganizationPipeline Organization Srom InterfaceStage 0 Instruction Fetch Stage 1 Instruction Slot14Internal Architecture Stage 2 Map Stage 3 IssueEbox and Fbox pipelines begin execution Instruction Issue RulesInstruction Issue Rules Pipeline AbortsInstruction Name, Pipeline, and Types Instruction Issue Rules Instruction Group DefinitionsInstruction Group Definitions and Pipeline Unit Ebox SlottingFTOIS, Ftoit ITOFS, ITOFF, ItoftU U L E L U E E L L E U 20Internal Architecture Instruction Issue Rules Instruction LatenciesInstruction Class Latency in Cycles HwmfprInstruction Retire Rules Instruction Retire RulesMinimum Retire Latencies for Instruction Classes BSR/JSR Retire of Operate Instructions into R31/F31Retire of Operate Instructions into R31/F31 Floating-Point Divide/Square Root Early RetireInstructions Retired Without Execution Load Instructions to R31 and F31Load Instructions to R31 and F31 Prefetch with Modify Intent LDS Instruction24Internal Architecture Special Cases of Alpha Instruction ExecutionPrefetch with the LDxL / STxC Instruction Sequence Load Hit SpeculationPipeline Timing for Integer Load Instructions Special Cases of Alpha Instruction ExecutionFloating-Point Store Instructions Cmov Instruction26Internal Architecture Memory and I/O Address Space Instructions Memory and I/O Address Space InstructionsMemory Address Space Load Instructions 2 I/O Address Space Load Instructions Rules for I/O Address Space Load Instruction Data Merging28Internal Architecture 4 I/O Address Space Store Instructions 8shows some of the following rulesRules for I/O Address Space Store Instruction Data Merging MAF Merging Rules MAF Memory Address Space Merging RulesInstruction Ordering MAF Memory Address Space Merging Rules10 Memory Reference Ordering Replay TrapsReplay Traps Mbox Order TrapsMemory Barrier MB/WMB/TB Fill Flow 12 I/O Write Buffer and the WMB InstructionWrite Buffer and the WMB Instruction Other Mbox Replay TrapsMB Instruction Processing 34Internal Architecture WMB Instruction ProcessingTB Fill Flow 12 TB Fill Flow Example Sequence13 TB Fill Flow Example Sequence Floating-point control register Fpcr is shown in Figure Performance Measurement Support-Performance CountersFloating-Point Control Register Performance Measurement Support-Performance CountersFloating-Point Control Register Implver Amask and Implver Instruction ValuesAmask and Implver Instruction Values AmaskDesign Examples Design Examples40Internal Architecture 13 Typical Multiprocessor Configuration21264/EV67 Microprocessor Logic Symbol Hardware InterfaceHardware Interface 21264/EV67 Microprocessor Logic Symbol 21264/EV67 Microprocessor Logic Symbol21264/EV67 Signal Descriptions 21264/EV67 Signal Names and Functions21264/EV67 Signal Names and Functions Signal Pin Types DefinitionsDcokh Pllvdd TestStatH 21264/EV67 Signal Descriptions by FunctionSysVref Domain SysAddInL140 Pin List Sorted by Signal Name Pin AssignmentsPin Assignments AC1 Pllvdd 10Hardware InterfaceAA5 12Hardware Interface Pin List Sorted by PGA LocationSysDataL28 14Hardware Interface BcDataH70 SysDataL5 16Hardware Interface Ground and Power VSS and VDD Pin ListMechanical Specifications Mechanical Specifications21264/EV67 Packaging 21264/EV67 Packaging18Hardware Interface 21264/EV67 Bottom View Pin Up Page Cache and External Interfaces Introduction to the External InterfacesCache and External Interfaces Introduction to the External Interfaces 21264/EV67 System and Bcache Interfaces System InterfaceSecond-Level Cache Bcache Interface Commands and AddressesPhysical Address Considerations Physical Address ConsiderationsMB/WMB ECB I/OPhysical Address Considerations System Duplicate Tag Stores Bcache Interface SignalsBcache Structure Bcache StructureCache Coherency Basics Victim Data BufferCache Coherency Victim Data Buffer21264/EV67-Supported Cache Block States Cache CoherencyCache Block States 2lists the cache block states supported by the 21264/EV6710Cache and External Interfaces System Responses to 21264/EV67 CommandsCache Block State Transitions Cache Block State TransitionsCache Coherency Using SysDc Commands 12Cache and External Interfaces Dcache States and Duplicate Tags Lock Mechanism Lock Mechanism14Cache and External Interfaces Liveness and Fairness Internal Eviction of LDxL BlocksSystem Port System Port16Cache and External Interfaces System Port Pins System Port Pins18Cache and External Interfaces System Port Programming the System Interface ClocksProgramming Values for System Interface Clocks Program Values for Data-Sample/Drive CSRs3 21264/EV67-to-System Commands Bank Interleave on Cache Block Boundary ModeForwarded Clocks and Frame Clock Ratio 12describes the field definitions for Tables 4-10and Hit Mode11 Page Hit Mode of Operation 12 21264/EV67-to-System Command Fields Definitions13 Maximum Physical Address for Short Bus Format 4 21264/EV67-to-System Commands Descriptions14describes the 21264/EV67-to-system commands 14 21264/EV67-to-System Commands Descriptions22Cache and External Interfaces 15 Programming INVALTODIRTYENABLE10 24Cache and External Interfaces ProbeResponse Commands Command40 =16 Programming SETDIRTYENABLE20 17 21264/EV67 ProbeResponse CommandSysAck and 21264/EV67-to-System Commands Flow Control 18describes the ProbeResponse command fields18 ProbeResponse Fields Descriptions RVB RPB System-to-21264/EV67 CommandsProbe Commands Four Cycles 19 System-to-21264/EV67 Probe Commands21 Data Movement Selection by Probe43 20 System-to-21264/EV67 Probe Commands Fields Descriptions21 lists the data movement selected by Probe43 22lists the next cache block state selected by Probe20Data Transfer Commands Two Cycles 23 Data Transfer Command Format28Cache and External Interfaces 24 SysDc40 Field Description 24describes the SysDc40 fieldData Movement In and Out of the 21264/EV67 8.1 21264/EV67 Clock Basics30Cache and External Interfaces Fast Data Mode 32Cache and External Interfaces 25 Sysclk Cycles Between SysAddOut and SysData26shows four example configurations and shows their use 26 Cbox CSR SYSDCDELAY40 ExamplesFast Data Disable Mode 34Cache and External Interfaces 27 Four Timing ExamplesSysDataInValidL and SysDataOutValidL SysDataInValidLSysFillValidL SysDataOutValidLData Wrapping 28 Data Wrapping Rules36Cache and External Interfaces 30defines the interleaved scheme for the wrap order 29 System Wrap and Deliver Data30 Wrap Interleave Order 38Cache and External Interfaces Nonexistent Memory Processing31defines the wrap order for double-pumped data transfers 31 Wrap Order for Double-Pumped Data Transfers21264/EV67 Command NXM Address System/21264/EV67 Response 10.1 21264/EV67 Commands and System Probes Ordering of System Port Transactions40Cache and External Interfaces System Port Bcache Port Bcache PortBcache Port Pins 36 Bcache Port Pins35 Range of Maximum Bcache Clock Ratios 44Cache and External Interfaces Bcache Clocking37 BCCPUCLKDELAY10 Values 38 BCCLKDELAY10 ValuesSetting the Period of the Cache Clock 46Cache and External Interfaces 39 Program Values to Set the Cache Clock Period Single-DataBcache Transactions 41 Data-Sample/Drive Cbox CSRsBcache Data Read and Tag Read Transactions 48Cache and External Interfaces Bcache Data Write TransactionsDual-data mode, bcfrm is twice the ratio When the ratio is even, bcfrm is equal to the ratioWhen the ratio is odd, bcfrm is twice the ratio For example, in single-data mode50Cache and External Interfaces BcAddH234 Pin DescriptionsRelationship Between Write-to-Read Bcwrrdbubbles and wrrd Relationship Between Read-to-Write Bcrdwrbubbles and rdwr44lists the combination of control pin assertion for 46 Control Pin Assertion for Ramtype C 47 Control Pin Assertion for Ramtype DBcDataInClkH and BcTagInClkH 54Cache and External Interfaces InterruptsInterrupts Bcache Banking Disabling the Bcache for DebuggingInternal Processor Registers Internal Processor RegistersMbox IPRs Cycle Counter Control Register Ccctl Ebox IPRsEbox IPRs Cycle Counter Register CCCycle Counter Control Register Fields Description Virtual Address Register VAVirtual Address Control Register Vactl 2describes the Ccctl register fieldsVAFORM32 Virtual Address Format Register Vaform3describes the virtual address control register fields Virtual Address Control Register Fields DescriptionITB PTE Array Write Register Itbpte Ibox IPRsIbox IPRs ITB Tag Array Write Register ItbtagITB Invalidate All Process ASM=0 Register Itbiap ITB Invalidate All Register ItbiaITB Invalidate Single Register Itbis ProfileMe PC Fields Description Ibox IPRs ProfileMe PC Register PmpcException Address Register Excaddr 4describes the ProfileMe PC register fields13shows Ivaform when ICTLVA48 equals 0 ICTLVAFORM32 equals Interrupt Enable and Current Processor Mode Register IercmSoftware Interrupt Request Register Sirr Iercm Register Fields Description10Internal Processor Registers Interrupt Summary Register Isum 6describes the software interrupt request register fieldsSoftware Interrupt Request Register Fields Description 12Internal Processor Registers Hardware Interrupt Clear Register Hwintclr7describes the interrupt summary register fields Interrupt Summary Register Fields DescriptionMchkd W1C Exception Summary Register Excsum8describes the hardware interrupt clear register fields Hardware Interrupt Clear Register Fields Description9describes the exception summary register fields Exception Summary Register Fields Description14Internal Processor Registers 10 PAL Base Register Fields Description PAL Base Register PalbaseIbox Control Register Ictl 10describes the PAL base register fields11describes the Ibox control register fields 11 Ibox Control Register Fields Description16Internal Processor Registers PCT1EN SingleissuehMchken STWAIT64KIbox Status Register Istat Spce18Internal Processor Registers TRP 12describes the Ibox status register fields12 Ibox Status Register Fields Description MIS20Internal Processor Registers Clear Virtual-to-Physical Map Register Clrmap Sleep Mode Register SleepIbox IPRs Icache Flush Register Icflush Icache Flush ASM Register Icflushasm14describes the process context register fields 14 Process Context Register Fields Description22Internal Processor Registers Performance Counter Control Register Pctrctl FPEPpce 15describes the performance counter control register fields 15 Performance Counter Control Register Fields Description24Internal Processor Registers 16 Performance Counter Control Register Input Select Fields Mbox IPRsMbox IPRs DTB Tag Array Write Registers 0 and 1 DTBTAG0, DTBTAG126Internal Processor Registers DTB Alternate Processor Mode Register DtbaltmodeDstream TB Invalidate Single Registers 0 and 1 DTBIS0,1 17 DTB Alternate Processor Mode Register Fields DescriptionDstream TB Invalidate All Process ASM=0 Register Dtbiap Dstream TB Invalidate All Register Dtbia28Internal Processor Registers Memory Management Status Register Mmstat18describes the memory management status register fields 18 Memory Management Status Register Fields DescriptionMbox Control Register Mctl ForACV 19 Mbox Control Register Fields Description Erences to superpages result in access violationsDcache Control Register Dcctl 19describes the Mbox control register fieldsDcache Status Register Dcstat 20describes the Dcache control register fields20 Dcache Control Register Fields Description 21 Dcache Status Register Fields Description Cbox CSRs and IPRsCbox CSRs and IPRs 21describes the Dcache status register fields22 describes the Cbox data register fields Cbox CSRs and IPRs Cbox Data Register CdataCbox Shift Register Cshft Cbox Writeonce Chain Description34Internal Processor Registers 24 Cbox Writeonce Chain OrderSkewedfillmode Mboxbcprbstall BCLATDATAPATTERN031 BCLATTAGPATTERN02336Internal Processor Registers SYSCLKDELAY10 38Internal Processor Registers Cbox Writemany Chain Description25 Cbox Writemany Chain Order 25describes the Cbox Writemany chain order from LSB to MSB40Internal Processor Registers Setdirtyenable = Bcbankenable =26 Cbox Read IPR Fields Description Cbox CSRs and IPRs Cbox Read Register IPR DescriptionPage Privileged Architecture Library Code PALcode DescriptionPrivileged Architecture Library Code PALmode Environment PALmode EnvironmentHwld Instruction Required PALcode Function CodesOpcodes Reserved for PALcode Required PALcode Function CodesHwld Instruction Fields Descriptions Opcodes Reserved for PALcodeHwst Instruction 3describes the Hwld instruction fieldsHwret Instruction 4describes the Hwst instruction fieldsHwst Instruction Fields Descriptions Hint Hwmfpr and Hwmtpr Instructions5describes the Hwret instruction fields Hwret Instruction Fields DescriptionsHwmfpr and Hwmtpr Instructions Fields Descriptions Internal Processor Register Access MechanismsInternal Processor Register Access Mechanisms 6describes the Hwmfpr and Hwmtpr instructions fieldsHardware Structure of Explicitly Written IPRs Paired Instruction Fetch Order IPR Access Ordering10Privileged Architecture Library Code PALcode Emulation of the Fpcr PALshadow RegistersPALcode Entry Points PALcode Exception Entry Locations PALcode Exception Entry Points14Privileged Architecture Library Code Translation Buffer TB Fill FlowsTranslation Buffer TB Fill Flows DTB FillWr Data Tb missWr PTE LD-PTE, write TB 16Privileged Architecture Library Code ITB FillPerformance Counter Support Performance Counter SupportIPRs Used for Performance Counter Support General PrecautionsAggregate Mode Programming Guidelines Aggregate Mode PrecautionsSL1 10 Aggregate Mode Returned IPR ContentsOperation Pctrctl SL0ProfileMe Mode Programming Guidelines 11shows the counter modes that are used with Aggregate modeThis input counts Mbox replay traps 12 Cmov Decomposed 22Privileged Architecture Library Code 13 ProfileMe Mode Returned IPR ContentsInum retire delay cycles ProfileMe Counting Mode Description Cycle counting24Privileged Architecture Library Code 14shows the counter modes that are used with ProfileMe modeCounter Modes for ProfileMe Mode 14 ProfileMe Mode Pctrctl Input Select FieldsInitialization and Configuration Initialization and ConfigurationPower-Up Reset Flow and the ResetL and Dcokh Pins 21264/EV67 Reset State Machine Major OperationsConstraints Power-Up Reset Flow and the ResetL and Dcokh PinsSignal Pin Reset State Power Sequencing and Reset State for Signal PinsPllvdd Clock Forwarding and System Clock Ratio ConfigurationPLL Pin Signal Names and Initialization StateBiST and Srom Load and the TestStatH Pin PLL Ramp UpPower-Up Flow Signals and Their Constraints Clock Forward Reset and System Interface InitializationFault Reset Flow Fault Reset FlowEffect on IPRs After Fault Reset Energy Star Certification and Sleep Mode Flow Energy Star Certification and Sleep Mode Flow10Initialization and Configuration Effect on IPRs After Transition Through Sleep ModeEffect on IPRs After Warm Reset Warm Reset FlowWarm Reset Flow Signals and Constraints for the Sleep Mode SequenceArray Initialization Initialization Mode Processing12Initialization and Configuration Array InitializationEVICTENABLE0 Initialization Mode ProcessingExternal Interface Initialization Internal Processor Register Power-Up Reset State10 Internal Processor Registers at Power-Up Reset State 14Initialization and ConfigurationInternal Processor Register Power-Up Reset State 16Initialization and Configuration Ieee 1149.1 Test Port ResetReset State Machine Ieee 1149.1 Test Port Reset11 21264/EV67 Reset State Machine State Descriptions Reset State Machine18Initialization and Configuration PLL Output Clocks Phase-Lock Loop PLL Functional DescriptionPhase-Lock Loop PLL Functional Description Differential Reference Clocks20Initialization and Configuration Power-Up/Reset ClockingError Detection and Error Handling 21264/EV67 Error Detection MechanismsError Detection and Error Handling Data Error Correction Code Data Error Correction CodeIcache Data or Tag Parity Error Dcache Tag Parity ErrorDcache Data Single-Bit Correctable ECC Error Dcache Data Single-Bit Correctable ECC ErrorLoad Instruction Store Instruction Quadword or Smaller Dcache Store Second ErrorDcache Duplicate Tag Parity Error Dcache Store Second ErrorIcache Fill from Bcache Bcache Tag Parity ErrorBcache Data Single-Bit Correctable ECC Error Bcache Tag Parity ErrorBcache Victim Read During a Dcache/Bcache Miss Bcache Victim ReadDcache Fill from Memory Memory/System Port Single-Bit Data Correctable ECC ErrorMemory/System Port Single-Bit Data Correctable ECC Error Icache Fill from MemoryBcache Data Single-Bit Correctable ECC Error on a Probe Bcache Data Single-Bit Correctable ECC Error on a Probe3summarizes the various error cases and their ramifications Double-Bit Fill ErrorsError Case Summary Double-Bit Fill Errors10Error Detection and Error Handling Error Case SummaryMchk Cstatdstreambcdbl Mchk CstatistreammemdblMchk Cstatdstreammemdbl Page Maximum Electrical Ratings Electrical CharacteristicsElectrical Data 1lists the maximum electrical ratings for the 21264/EV67Idcpower DC CharacteristicsDC Characteristics Signal TypesInput Differential Amplifier Clock Receiver Idaclk VDD IdcpowerInput DC Reference Pin Idcref Input Differential Amplifier Receiver IDACodtp Pin Type Open-Drain Driver for Test Pins OodtpPin Type Open-Drain Output Driver OOD IOZ12 Push-Pull Output Clock Driver Oppclk 11 Push-Pull Output Driver OPPAC Characteristics AC CharacteristicsAC Test Conditions TSU TDH 13 AC SpecificationsTSU1 TDH2 AC Characteristics Page Thermal Management Operating TemperatureAmbient temperature requirement Operating Temperature at Heat Sink Center TcOperating Temperature Θca at Various Airflows for 21264/EV6710-2Thermal Management Heat Sink Specifications Heat Sink Specifications10-4Thermal Management Type 1 Heat SinkType 2 Heat Sink 10-6Thermal Management Type 3 Heat SinkThermal Design Considerations Thermal Design ConsiderationsPage Testability and Diagnostics Testability and DiagnosticsTest Pins Dedicated Test Port PinsSrom Load Operation SROM/Serial Diagnostic Terminal PortSROM/Serial Diagnostic Terminal Port 11-2Testability and DiagnosticsIeee 1149.1 Port Ieee 1149.1 PortIeee 1149.1 Instructions and Opcodes 11-4Testability and Diagnostics TestStatH PinTestStatH Pin Srom Initialization Power-Up Self-Test and InitializationPower-Up Self-Test and Initialization Built-in Self-TestSerial Instruction Cache Load Operation 11-6Testability and DiagnosticsSee Appendix B for a listing of the Boundary-Scan Register Icache Bit Fields in an Srom LineReferences Page Alpha Instruction Set A-1 Alpha Instruction SetAlpha Instruction Summary Table A-1 Instruction Format and Opcode NotationAlpha Instruction Summary Opr 11.46 Cmove if ≥ zero Mbr Branch to subroutinePcd Trap to PALcode Opr 11.24 Cmove if = zero15.0BE Convert quadword to Gfloating 15.0AF Convert Gfloating to quadword17.010 Convert longword to quadword 15.0BC Convert quadword to Ffloating17.02B Fcmove if ≠ zero 17.02F Fcmove if zero17.02E Fcmove if ≤ zero 17.02C Fcmove if zeroMem Load Sfloating Opr 13.40 Multiply longword with integer overflow enableOpr 13.60 Multiply quadword with integer overflow enable Opr 1C.31 Pixel errorOpr 10.02 Scaled add longword by Opr 1C.36 Pack words to bytes Mfc 18.E000 Read and clearMbr 1A.2 Return from subroutine Mfc 18.C000 Read process cycle counter 18.F000 Read and setReserved Opcodes Reserved OpcodesOpcodes Reserved for Compaq Ieee Floating-Point Instructions Ieee Floating-Point Instructions VAX Floating-Point Instructions Independent Floating-Point InstructionsVAX Floating-Point Instructions Opcode Summary Opcode SummaryFloating-point operate instruction opcodes Mem Table A-9explains the symbols used in Table A-8Mem Res Ieee floating-point instruction opcodesIeee Floating-Point Conformance Ieee Floating-Point Conformance14Alpha Instruction Set Alpha Instruction Set A-15 Table A-11 Exceptional Input and Output ConditionsCmpteq Cmptun Input Cmptlt Cmptle Input16Alpha Instruction Set Alpha Instruction Set A-17 Fbeq Fbne Fblt Fble Fbgt Fbge LDS LDT STS STT Cpys CpysnPage Boundary-Scan Register 21264/EV67 Boundary-Scan RegisterPllvdd Boundary-Scan Register21264/EV67 Boundary-Scan Register B-3 421264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B-5 621264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B-7 821264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B-9 1021264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B-11 1221264/EV67 Boundary-Scan Register Serial Icache Load Predecode Values C-1 Serial Icache Load Predecode ValuesPage PALcode Restrictions and Guidelines D-1 PALcode Restrictions and Guidelines2PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-3 4PALcode Restrictions and Guidelines Initwritemany PALcode Restrictions and Guidelines D-56PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-7 8PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-9 Restriction 7 Replay Trap, Interrupt Code Sequence, and STF10PALcode Restrictions and Guidelines Restriction 10 Duplicate IPR Mode BitsRestriction 9 PALmode Istream Address Ranges Restriction 9 PALmode Istream Address RangesRestriction 14 Hwret Restriction 11 Ibox IPR Update SynchronizationRestriction 11 Ibox IPR Update Synchronization Restriction 13 DTB Fill Flow CollisionGuideline 16 JSR-BAD VA Guideline 20 Ictlsbe Stream Buffer EnableGuideline 16 JSR-BAD VA Restriction 21 HWRET/STALL After Hwmtpr ASN0/ASN1Restriction 22 HWRET/STALL After Hwmtpr IS0/IS1 Restriction 22 HWRET/STALL After Hwmtpr IS0/IS1PALcode Restrictions and Guidelines D-13 14PALcode Restrictions and Guidelines Restriction 25 Hwmtpr Itbia After ResetGuideline 26 Conditional Branches in PALcode Restriction 24 HWRET/STALL After Hwmtpr ICFLUSH, IcflushasmGuideline 29 JSR, JMP, RET, and Jsrcor in PALcode Restriction 30 Hwmtpr and Hwmfpr to the Cbox CSRPALcode Restrictions and Guidelines D-15 16PALcode Restrictions and Guidelines Restriction 30 Hwmtpr and Hwmfpr to the Cbox CSRPALcode Restrictions and Guidelines D-17 Restriction 31 ICTLVA48 UpdateRestriction 32 Pctrctl Update Restriction 31 ICTLVA48 UpdateRestriction 37 Updating VACTLVA48 Guideline 35 Hwintclr UpdateRestriction 33 Hwld Physical/Lock Use Restriction 36 Updating IctlsdePALcode Restrictions and Guidelines D-19 Restriction 40 Scrubbing a Single-Bit Error20PALcode Restrictions and Guidelines Restriction 40 Scrubbing a Single-Bit ErrorRestriction 42 Updating VACTL, CCCTL, or CC IPRs Restriction 43 No Trappable Instructions Along withPALcode Restrictions and Guidelines D-21 22PALcode Restrictions and Guidelines Restriction 47 Cache Eviction for Single-Bit Cache ErrorsPALcode Restrictions and Guidelines D-23 Restriction 47 Cache Eviction for Single-Bit Cache Errors24PALcode Restrictions and Guidelines 21264/EV67-to-Bcache Pin Interconnections Forwarding Clock Pin GroupingsTable E-1 Bcache Forwarding Clock Pin Groupings Tag Pin Usage Late-Write Non-Bursting SSRAMsLate-Write Non-Bursting SSRAMs Data Pin UsageTable E-4 Dual-Data Rate Ssram Data Pin Usage Dual-Data Rate SSRAMsDual-Data Rate SSRAMs Data and Tag Pin UsageTable E-5 Dual-Data Rate Ssram Tag Pin Usage TrstlGlossary BIU BSR Cisc CSR CmosCPI CPUDTL DMADram DTBFpga FepromFET FEUIDU GclkJfet IowbIpga ITBMips MAFMBO MBZNvram MSINaturally Aligned NmosPlcc PALPGA PLARAS PqfpProm RAMSAM RiscROM RTLSipp SdramSimm SIPUnaligned StramTTL UartVDF UnpredictableUvprom VAFWriteblock WARNumerics IndexIndex-2 Index-3 Index-4 ECC Index-6 Index-7 Index-8 Index-9 Index-10 Index-11 Index-12