Compaq 21264, EV67 specifications Internal Processor Registers

4.3.2	System Duplicate Tag Stores	4–7
4.4	Victim Data Buffer	4–8
4.5	Cache Coherency	4–8
4.5.1	Cache Coherency Basics	4–8
4.5.2	Cache Block States	4–9
4.5.3	Cache Block State Transitions	4–10
4.5.4	Using SysDc Commands	4–11
4.5.5	Dcache States and Duplicate Tags	4–13
4.6	Lock Mechanism	4–14
4.6.1	In-Order Processing of LDx_L/STx_C Instructions	4–15
4.6.2	Internal Eviction of LDx_L Blocks	4–15
4.6.3	Liveness and Fairness	4–15
4.6.4	Managing Speculative Store Issues with Multiprocessor Systems	4–16
4.7	System Port	4–16
4.7.1	System Port Pins	4–17
4.7.2	Programming the System Interface Clocks	4–18
4.7.3	21264/EV67-to-System Commands	4–19
4.7.3.1	Bank Interleave on Cache Block Boundary Mode	4–19
4.7.3.2	Page Hit Mode	4–20
4.7.4	21264/EV67-to-System Commands Descriptions	4–21
4.7.5	ProbeResponse Commands (Command[4:0] = 00001)	4–24
4.7.6	SysAck and 21264/EV67-to-System Commands Flow Control	4–25
4.7.7	System-to-21264/EV67 Commands	4–26
4.7.7.1	Probe Commands (Four Cycles)	4–26
4.7.7.2	Data Transfer Commands (Two Cycles)	4–28
4.7.8	Data Movement In and Out of the 21264/EV67	4–30
4.7.8.1	21264/EV67 Clock Basics	4–30
4.7.8.2	Fast Data Mode	4–31
4.7.8.3	Fast Data Disable Mode	4–33
4.7.8.4	SysDataInValid_L and SysDataOutValid_L	4–34
4.7.8.5	SysFillValid_L	4–35
4.7.8.6	Data Wrapping	4–36
4.7.9	Nonexistent Memory Processing	4–38
4.7.10	Ordering of System Port Transactions	4–40
4.7.10.1	21264/EV67 Commands and System Probes	4–40
4.7.10.2	System Probes and SysDc Commands	4–42
4.8	Bcache Port	4–42
4.8.1	Bcache Port Pins	4–43
4.8.2	Bcache Clocking	4–44
4.8.2.1	Setting the Period of the Cache Clock	4–45
4.8.3	Bcache Transactions	4–47
4.8.3.1	Bcache Data Read and Tag Read Transactions	4–47
4.8.3.2	Bcache Data Write Transactions	4–48
4.8.3.3	Bubbles on the Bcache Data Bus	4–49
4.8.4	Pin Descriptions	4–51
4.8.4.1	BcAdd_H[23:4]	4–51
4.8.4.2	Bcache Control Pins	4–52
4.8.4.3	BcDataInClk_H and BcTagInClk_H	4–53
4.8.5	Bcache Banking	4–54
4.8.6	Disabling the Bcache for Debugging	4–54
4.9	Interrupts	4–54

5 Internal Processor Registers

5.1	Ebox IPRs	5–3
5.1.1	Cycle Counter Register – CC	5–3
5.1.2	Cycle Counter Control Register – CC_CTL	5–3

Alpha 21264/EV67 Hardware Reference Manual v