Compaq 21264, EV67 specifications Dcache States and Duplicate Tags

Cache Coherency

Table 4–5 System Responses to 21264/EV67 Commands and 21264/EV67 Reactions (Continued)

21264/EV67
CMD	SysDc	21264/EV67 Action
InvalToDirty	ChangeToDirtyFail	Illegal. InvalToDirty instructions must provide a cache block.
Fetchx	ReadData	The 21264/EV67 delivers the data block, independent of its
Rdiox	ReadDataShared	status, to waiting load instructions and does not cache the block in the
	ReadDataShared/Dirty	21264/EV67 cache system.
	ReadDataDirty
Fetchx	ReadDataError	The cache block address was to an NXM address space. The 21264/
		EV67 delivers the all-ones patterns to any dependent load instructions
		and does not cache the block in the 21264/EV67 cache system.
Rdiox	ReadDataError	The cache block access was to NXM address space. The 21264/EV67
		delivers an all-ones pattern to any load command and does not cache
		the block in the 21264/EV67 cache system.
Evict	ChangeToDirtyFail	Retiring the MAF entry is the only legal response.
STCChangeTo	ReadDataX	All fill and ChangeToDirtyFail responses will fail the STx_C require-
Dirty	ChangeToDirtyFail	ments.
STCChangeTo	ChangeToDirtySuccess	The STx_C instruction succeeds.
Dirty
MB	MBDone	Acknowledgment for MB.

The 21264/EV67 sends a WrVictimBlk command to the system when it evicts a Dirty or Dirty/Shared cache block. The 21264/EV67 may be configured to send a CleanVic- timBlk to the system (by way of the Cbox CSR BC_CLEAN_VICTIM[0]) when evict- ing a clean or shared block. Both commands allocate buffers in the VAF (victim address file). This buffer is a coherent part of the 21264/EV67 cache system. Write data control and deallocation of the VAF can be directly controlled by using the SysDc WriteData and ReleaseBuffer commands.

4.5.5 Dcache States and Duplicate Tags

Each Dcache block contains an extra state bit (modified bit), beyond those required to support the cache protocol. If set, this bit indicates that the associated block should be written to the Bcache when it is evicted from the Dcache. The modified bit is set in two cases:

1.When a block is filled into the Dcache from memory its modified bit is set, ensur- ing that it also gets written back into the Bcache at some future time.

2.When the processor writes to a dirty Dcache block the modified bit is set, indicating it should be written to the Bcache when evicted.

The contents of the modified bit are functionally invisible to the external cache environ- ment, but knowledge of the bits function is useful to programmers optimizing the scheduling of the Bcache data bus.

The Cbox contains a duplicate copy of the Dcache tag array. In contrast to the Dcache tag array (DTAG), which is virtually indexed, the Cbox copy of the Dcache tag array (CTAG) is physically-indexed. The Cbox uses the CTAG array entries in the following situations.

Alpha 21264/EV67 Hardware Reference Manual Cache and External Interfaces 4–13