Compaq EV67, 21264 specifications Index-4

Dcache

described, 2–12

duplicate tag parity errors, 8–4duplicate tags with, 4–13error case summary for, 8–9fill from Bcache error, 8–6fill from memory errors, 8–7initialized by BiST, 7–12pipelined, 2–16

single-bit correctable ECC error, 8–3store second error, 8–4

tag parity errors, 8–2victim extracts, 8–4

Dcache data single-bit correctable ECC errors, 8–3

Dcache tag, initialized by BiST, 7–12

DCOK_H signal pin, 3–4power-on reset flow, 7–1

DCVIC_THRESHOLD Cbox CSR, defined, 5–34

DFAULT fault, 6–13

Differential 21264/EV67 clocks, 7–19

Differential reference clocks, 7–19

Dirty cache block state, 4–10

Dirty/Shared cache block state, 4–10

Do not care convention, xxi

Double-bit fill errors, 8–9

DOWN1 reset machine state, 7–18

DOWN2 reset machine state, 7–19

DOWN3 reset machine state, 7–19

Dstream translation buffer, 2–13 See also DTB

DSTREAM_BC_DBL error status in C_STAT, 5–41

DSTREAM_BC_ERR error status in C_STAT, 5–41

DSTREAM_DC_ERR error status in C_STAT, 5–41

DSTREAM_MEM_DBL error status in C_STAT, 5–41

DSTREAM_MEM_ERR error status in C_STAT, 5–41

DTAG. See Duplicate Dcache tag array

DTB entries, writing multiple in same PAL flow, D–19

DTB fill, 6–14

DTB, pipeline abort delay with, 2–16

DTB_ALTMODE alternate processor mode register, 5–26

at power-on reset state, 7–15

DTB_ASN0 address space number register 0 at power-on reset state, 7–16

DTB_ASN0 address space number registers 0, 5–28

DTB_ASN1 address space number register 1, 5–28at power-on reset state, 7–16

DTB_IA invalidate-all process register, 5–27at power-on reset state, 7–15

DTB_IAP invalidate-all (ASM=0) process register, 5–27

at power-on reset state, 7–15

DTB_IS0 invalidate single (array 0) register, 5–27at power-on reset state, 7–16

DTB_IS1 invalidate single (array 1) register, 5–27at power-on reset state, 7–16

DTB_PTE0 array write 0 register

at power-on reset state, 7–15MTPR to, D–12

DTB_PTE0 array write register 0, 5–26

DTB_PTE1 array write 1 register, 5–26

at power-on reset state, 7–15MTPR to, D–12

DTB_TAG0 array write 0 register, 5–25

at power-on reset state, 7–15MTPR to, D–12

DTB_TAG1 array write 1 register, 5–25

at power-on reset state, 7–15MTPR to, D–12

DTBM_DOUBLE_3 fault, 6–13

DTBM_DOUBLE_4 fault, 6–13

DTBM_SINGLE fault, 6–13

Dual-data rate SSRAM pin assignments, E–3

DUP_TAG_ENABLE Cbox CSR, defined, 5–34

Duplicate Dcache tag array, 2–11

Duplicate Dcache, initialized by BiST, 7–12

Duplicate tag array, Cbox copy. See CTAG

Duplicate tag stores, Bcache, 4–7

E

Ebox

cycle counter control register CC_CTL, 5–3cycle counter register CC, 5–3described, 2–8

executed in pipeline, 2–16internal processor registers, 5–1slotting, 2–18

subclusters, 2–18

virtual address control register VA_CTL, 5–4virtual address format register VA_FORM, 5–5virtual address register, 5–4

ECB instruction, external interface reference, 4–5

Index–4 Alpha 21264/EV67 Hardware Reference Manual