Hardware Reference Manual
Revision/Update Information
Alpha 21264A Microprocessor
DS-0028A-TE
Alpha 21264/EV67 Hardware Reference Manual
Table of Contents
Hardware Interface
Cache and External Interfaces
Internal Processor Registers
Privileged Architecture Library Code
Initialization and Configuration
Mffpcr Mtfpcr
Electrical Data
Error Detection and Error Handling
Testability and Diagnostics
Thermal Management
Alpha Instruction Set
21264/EV67 Boundary-Scan Register
21264/EV67-to-Bcache Pin Interconnections
Glossary Index
Figures
Xii
Tables
Xiv
VDD Idcpower
Page
Preface
Content
Audience
Documentation Included by Reference
For example
Terminology and Conventions
Abbreviations
Addresses
W1C
W1S
Aligned and Unaligned
Do Not Care
Signal Names
Data Units
External
Undefined
Do not care. a capital X represents any valid value
Page
Architecture
Introduction
Introduction
Integer Data Types
Architecture
Addressing
Floating-Point Data Types
21264/EV67 Microprocessor Features
21264/EV67 Microprocessor Features
21264/EV67 Microprocessor Features
21264/EV67 Microarchitecture
Internal Architecture
Internal Architecture
21264/EV67 Microarchitecture
Instruction Fetch, Issue, and Retire Unit
Virtual Program Counter Logic
21264/EV67 Block Diagram
Branch Predictor
Local Predictor
Global Predictor
Choice Predictor
Instruction-Stream Translation Buffer
Instruction Fetch Logic
Integer Issue Queue
Register Rename Maps
Floating-Point Issue Queue
Hwret
Exception and Interrupt Logic
Integer Execution Unit
Retire Logic
PERR, MINxxx, MAXxxx, UNPKxx, PKxx
Integer Execution Unit-Clusters 0
Floating-Point Execution Unit
10Internal Architecture
Onchip Caches
External Cache and System Interface Unit
21264/EV67 contains two onchip primary-level caches
Data Cache
Memory Reference Unit
12Internal Architecture
Srom Interface
Pipeline Organization
Pipeline Organization
Miss address file MAF Dstream translation buffer DTB
Stage 1 Instruction Slot
Stage 0 Instruction Fetch
14Internal Architecture
Stage 3 Issue
Stage 2 Map
Pipeline Aborts
Instruction Issue Rules
Instruction Issue Rules
Ebox and Fbox pipelines begin execution
Instruction Issue Rules Instruction Group Definitions
Instruction Name, Pipeline, and Types
ITOFS, ITOFF, Itoft
Ebox Slotting
FTOIS, Ftoit
Instruction Group Definitions and Pipeline Unit
U U L E L U E E L L E U
Hwmfpr
Instruction Issue Rules Instruction Latencies
Instruction Class Latency in Cycles
20Internal Architecture
Instruction Retire Rules
Instruction Retire Rules
Minimum Retire Latencies for Instruction Classes
Floating-Point Divide/Square Root Early Retire
Retire of Operate Instructions into R31/F31
Retire of Operate Instructions into R31/F31
BSR/JSR
Prefetch with Modify Intent LDS Instruction
Load Instructions to R31 and F31
Load Instructions to R31 and F31
Instructions Retired Without Execution
Load Hit Speculation
Special Cases of Alpha Instruction Execution
Prefetch with the LDxL / STxC Instruction Sequence
24Internal Architecture
Special Cases of Alpha Instruction Execution
Pipeline Timing for Integer Load Instructions
Cmov Instruction
Floating-Point Store Instructions
26Internal Architecture
Memory and I/O Address Space Instructions
Memory and I/O Address Space Instructions
Memory Address Space Load Instructions
Rules for I/O Address Space Load Instruction Data Merging
2 I/O Address Space Load Instructions
28Internal Architecture
8shows some of the following rules
4 I/O Address Space Store Instructions
Rules for I/O Address Space Store Instruction Data Merging
MAF Memory Address Space Merging Rules
MAF Memory Address Space Merging Rules
Instruction Ordering
MAF Merging Rules
Mbox Order Traps
Replay Traps
Replay Traps
10 Memory Reference Ordering
Other Mbox Replay Traps
12 I/O Write Buffer and the WMB Instruction
Write Buffer and the WMB Instruction
Memory Barrier MB/WMB/TB Fill Flow
MB Instruction Processing
12 TB Fill Flow Example Sequence
WMB Instruction Processing
TB Fill Flow
34Internal Architecture
13 TB Fill Flow Example Sequence
Performance Measurement Support-Performance Counters
Performance Measurement Support-Performance Counters
Floating-Point Control Register
Floating-point control register Fpcr is shown in Figure
Floating-Point Control Register
Amask
Amask and Implver Instruction Values
Amask and Implver Instruction Values
Implver
Design Examples
Design Examples
13 Typical Multiprocessor Configuration
40Internal Architecture
Hardware Interface
21264/EV67 Microprocessor Logic Symbol
Hardware Interface
21264/EV67 Microprocessor Logic Symbol
21264/EV67 Microprocessor Logic Symbol
Signal Pin Types Definitions
21264/EV67 Signal Names and Functions
21264/EV67 Signal Names and Functions
21264/EV67 Signal Descriptions
Dcokh
Pllvdd
21264/EV67 Signal Descriptions by Function
TestStatH
SysVref Domain SysAddInL140
Pin Assignments
Pin List Sorted by Signal Name
Pin Assignments
AC1
10Hardware Interface
Pllvdd
AA5
Pin List Sorted by PGA Location
12Hardware Interface
SysDataL28
14Hardware Interface
BcDataH70 SysDataL5
Ground and Power VSS and VDD Pin List
16Hardware Interface
Mechanical Specifications
Mechanical Specifications
21264/EV67 Packaging
21264/EV67 Packaging
18Hardware Interface
21264/EV67 Bottom View Pin Up
Page
Introduction to the External Interfaces
Cache and External Interfaces
Cache and External Interfaces
Introduction to the External Interfaces
System Interface
21264/EV67 System and Bcache Interfaces
Physical Address Considerations
Commands and Addresses
Physical Address Considerations
Second-Level Cache Bcache Interface
ECB I/O
MB/WMB
Physical Address Considerations
Bcache Structure
Bcache Interface Signals
Bcache Structure
System Duplicate Tag Stores
Victim Data Buffer
Victim Data Buffer
Cache Coherency
Cache Coherency Basics
2lists the cache block states supported by the 21264/EV67
Cache Coherency
Cache Block States
21264/EV67-Supported Cache Block States
Cache Block State Transitions
System Responses to 21264/EV67 Commands
Cache Block State Transitions
10Cache and External Interfaces
Cache Coherency Using SysDc Commands
12Cache and External Interfaces
Dcache States and Duplicate Tags
Lock Mechanism
Lock Mechanism
14Cache and External Interfaces
Internal Eviction of LDxL Blocks
Liveness and Fairness
System Port
System Port
16Cache and External Interfaces
System Port Pins
System Port Pins
Program Values for Data-Sample/Drive CSRs
System Port Programming the System Interface Clocks
Programming Values for System Interface Clocks
18Cache and External Interfaces
Bank Interleave on Cache Block Boundary Mode
3 21264/EV67-to-System Commands
Forwarded Clocks and Frame Clock Ratio
12 21264/EV67-to-System Command Fields Definitions
Hit Mode
11 Page Hit Mode of Operation
12describes the field definitions for Tables 4-10and
14 21264/EV67-to-System Commands Descriptions
4 21264/EV67-to-System Commands Descriptions
14describes the 21264/EV67-to-system commands
13 Maximum Physical Address for Short Bus Format
22Cache and External Interfaces
15 Programming INVALTODIRTYENABLE10
17 21264/EV67 ProbeResponse Command
ProbeResponse Commands Command40 =
16 Programming SETDIRTYENABLE20
24Cache and External Interfaces
18describes the ProbeResponse command fields
SysAck and 21264/EV67-to-System Commands Flow Control
18 ProbeResponse Fields Descriptions
19 System-to-21264/EV67 Probe Commands
System-to-21264/EV67 Commands
Probe Commands Four Cycles
RVB RPB
22lists the next cache block state selected by Probe20
20 System-to-21264/EV67 Probe Commands Fields Descriptions
21 lists the data movement selected by Probe43
21 Data Movement Selection by Probe43
23 Data Transfer Command Format
Data Transfer Commands Two Cycles
28Cache and External Interfaces
24describes the SysDc40 field
24 SysDc40 Field Description
8.1 21264/EV67 Clock Basics
Data Movement In and Out of the 21264/EV67
30Cache and External Interfaces
Fast Data Mode
25 Sysclk Cycles Between SysAddOut and SysData
32Cache and External Interfaces
26 Cbox CSR SYSDCDELAY40 Examples
26shows four example configurations and shows their use
Fast Data Disable Mode
SysDataInValidL
27 Four Timing Examples
SysDataInValidL and SysDataOutValidL
34Cache and External Interfaces
SysDataOutValidL
SysFillValidL
28 Data Wrapping Rules
Data Wrapping
36Cache and External Interfaces
29 System Wrap and Deliver Data
30defines the interleaved scheme for the wrap order
30 Wrap Interleave Order
31 Wrap Order for Double-Pumped Data Transfers
Nonexistent Memory Processing
31defines the wrap order for double-pumped data transfers
38Cache and External Interfaces
21264/EV67 Command NXM Address System/21264/EV67 Response
Ordering of System Port Transactions
10.1 21264/EV67 Commands and System Probes
40Cache and External Interfaces
System Port
Bcache Port
Bcache Port
36 Bcache Port Pins
Bcache Port Pins
35 Range of Maximum Bcache Clock Ratios
Bcache Clocking
44Cache and External Interfaces
38 BCCLKDELAY10 Values
37 BCCPUCLKDELAY10 Values
Setting the Period of the Cache Clock
39 Program Values to Set the Cache Clock Period Single-Data
46Cache and External Interfaces
41 Data-Sample/Drive Cbox CSRs
Bcache Transactions
Bcache Data Read and Tag Read Transactions
Bcache Data Write Transactions
48Cache and External Interfaces
For example, in single-data mode
When the ratio is even, bcfrm is equal to the ratio
When the ratio is odd, bcfrm is twice the ratio
Dual-data mode, bcfrm is twice the ratio
50Cache and External Interfaces
Relationship Between Read-to-Write Bcrdwrbubbles and rdwr
Pin Descriptions
Relationship Between Write-to-Read Bcwrrdbubbles and wrrd
BcAddH234
44lists the combination of control pin assertion for
47 Control Pin Assertion for Ramtype D
46 Control Pin Assertion for Ramtype C
BcDataInClkH and BcTagInClkH
Disabling the Bcache for Debugging
Interrupts
Interrupts Bcache Banking
54Cache and External Interfaces
Internal Processor Registers
Internal Processor Registers
Mbox IPRs
Cycle Counter Register CC
Ebox IPRs
Ebox IPRs
Cycle Counter Control Register Ccctl
2describes the Ccctl register fields
Virtual Address Register VA
Virtual Address Control Register Vactl
Cycle Counter Control Register Fields Description
Virtual Address Control Register Fields Description
Virtual Address Format Register Vaform
3describes the virtual address control register fields
VAFORM32
ITB Tag Array Write Register Itbtag
Ibox IPRs
Ibox IPRs
ITB PTE Array Write Register Itbpte
ITB Invalidate All Register Itbia
ITB Invalidate All Process ASM=0 Register Itbiap
ITB Invalidate Single Register Itbis
4describes the ProfileMe PC register fields
Ibox IPRs ProfileMe PC Register Pmpc
Exception Address Register Excaddr
ProfileMe PC Fields Description
Interrupt Enable and Current Processor Mode Register Iercm
13shows Ivaform when ICTLVA48 equals 0 ICTLVAFORM32 equals
Iercm Register Fields Description
Software Interrupt Request Register Sirr
10Internal Processor Registers
6describes the software interrupt request register fields
Interrupt Summary Register Isum
Software Interrupt Request Register Fields Description
Interrupt Summary Register Fields Description
Hardware Interrupt Clear Register Hwintclr
7describes the interrupt summary register fields
12Internal Processor Registers
Hardware Interrupt Clear Register Fields Description
Exception Summary Register Excsum
8describes the hardware interrupt clear register fields
Mchkd W1C
Exception Summary Register Fields Description
9describes the exception summary register fields
14Internal Processor Registers
10describes the PAL base register fields
PAL Base Register Palbase
Ibox Control Register Ictl
10 PAL Base Register Fields Description
11 Ibox Control Register Fields Description
11describes the Ibox control register fields
16Internal Processor Registers
STWAIT64K
Singleissueh
Mchken
PCT1EN
Spce
Ibox Status Register Istat
18Internal Processor Registers
MIS
12describes the Ibox status register fields
12 Ibox Status Register Fields Description
TRP
20Internal Processor Registers
Icache Flush ASM Register Icflushasm
Sleep Mode Register Sleep
Ibox IPRs Icache Flush Register Icflush
Clear Virtual-to-Physical Map Register Clrmap
14 Process Context Register Fields Description
14describes the process context register fields
22Internal Processor Registers
FPE
Performance Counter Control Register Pctrctl
Ppce
15 Performance Counter Control Register Fields Description
15describes the performance counter control register fields
24Internal Processor Registers
DTB Tag Array Write Registers 0 and 1 DTBTAG0, DTBTAG1
Mbox IPRs
Mbox IPRs
16 Performance Counter Control Register Input Select Fields
DTB Alternate Processor Mode Register Dtbaltmode
26Internal Processor Registers
Dstream TB Invalidate All Register Dtbia
17 DTB Alternate Processor Mode Register Fields Description
Dstream TB Invalidate All Process ASM=0 Register Dtbiap
Dstream TB Invalidate Single Registers 0 and 1 DTBIS0,1
18 Memory Management Status Register Fields Description
Memory Management Status Register Mmstat
18describes the memory management status register fields
28Internal Processor Registers
For
Mbox Control Register Mctl
ACV
19describes the Mbox control register fields
Erences to superpages result in access violations
Dcache Control Register Dcctl
19 Mbox Control Register Fields Description
20describes the Dcache control register fields
Dcache Status Register Dcstat
20 Dcache Control Register Fields Description
21describes the Dcache status register fields
Cbox CSRs and IPRs
Cbox CSRs and IPRs
21 Dcache Status Register Fields Description
Cbox Writeonce Chain Description
Cbox CSRs and IPRs Cbox Data Register Cdata
Cbox Shift Register Cshft
22 describes the Cbox data register fields
24 Cbox Writeonce Chain Order
34Internal Processor Registers
Mboxbcprbstall BCLATDATAPATTERN031 BCLATTAGPATTERN023
Skewedfillmode
36Internal Processor Registers
SYSCLKDELAY10
Cbox Writemany Chain Description
38Internal Processor Registers
25describes the Cbox Writemany chain order from LSB to MSB
25 Cbox Writemany Chain Order
Setdirtyenable = Bcbankenable =
40Internal Processor Registers
Cbox CSRs and IPRs Cbox Read Register IPR Description
26 Cbox Read IPR Fields Description
Page
PALcode Description
Privileged Architecture Library Code
Privileged Architecture Library Code
PALmode Environment
PALmode Environment
Required PALcode Function Codes
Required PALcode Function Codes
Opcodes Reserved for PALcode
Hwld Instruction
3describes the Hwld instruction fields
Opcodes Reserved for PALcode
Hwst Instruction
Hwld Instruction Fields Descriptions
4describes the Hwst instruction fields
Hwret Instruction
Hwst Instruction Fields Descriptions
Hwret Instruction Fields Descriptions
Hwmfpr and Hwmtpr Instructions
5describes the Hwret instruction fields
Hint
6describes the Hwmfpr and Hwmtpr instructions fields
Internal Processor Register Access Mechanisms
Internal Processor Register Access Mechanisms
Hwmfpr and Hwmtpr Instructions Fields Descriptions
Hardware Structure of Explicitly Written IPRs
IPR Access Ordering
Paired Instruction Fetch Order
10Privileged Architecture Library Code
PALshadow Registers
PALcode Emulation of the Fpcr
PALcode Entry Points
PALcode Exception Entry Points
PALcode Exception Entry Locations
DTB Fill
Translation Buffer TB Fill Flows
Translation Buffer TB Fill Flows
14Privileged Architecture Library Code
Tb miss
Wr Data
Wr PTE LD-PTE, write TB
ITB Fill
16Privileged Architecture Library Code
Performance Counter Support
Performance Counter Support
Aggregate Mode Precautions
General Precautions
Aggregate Mode Programming Guidelines
IPRs Used for Performance Counter Support
Pctrctl SL0
10 Aggregate Mode Returned IPR Contents
Operation
SL1
11shows the counter modes that are used with Aggregate mode
ProfileMe Mode Programming Guidelines
This input counts Mbox replay traps
12 Cmov Decomposed
13 ProfileMe Mode Returned IPR Contents
22Privileged Architecture Library Code
ProfileMe Counting Mode Description Cycle counting
Inum retire delay cycles
14 ProfileMe Mode Pctrctl Input Select Fields
14shows the counter modes that are used with ProfileMe mode
Counter Modes for ProfileMe Mode
24Privileged Architecture Library Code
21264/EV67 Reset State Machine Major Operations
Initialization and Configuration
Power-Up Reset Flow and the ResetL and Dcokh Pins
Initialization and Configuration
Power-Up Reset Flow and the ResetL and Dcokh Pins
Constraints
Power Sequencing and Reset State for Signal Pins
Signal Pin Reset State
Clock Forwarding and System Clock Ratio Configuration
Pllvdd
Pin Signal Names and Initialization State
PLL
PLL Ramp Up
BiST and Srom Load and the TestStatH Pin
Clock Forward Reset and System Interface Initialization
Power-Up Flow Signals and Their Constraints
Fault Reset Flow
Fault Reset Flow
Effect on IPRs After Fault Reset
Energy Star Certification and Sleep Mode Flow
Energy Star Certification and Sleep Mode Flow
Effect on IPRs After Transition Through Sleep Mode
10Initialization and Configuration
Signals and Constraints for the Sleep Mode Sequence
Warm Reset Flow
Warm Reset Flow
Effect on IPRs After Warm Reset
Array Initialization
Initialization Mode Processing
12Initialization and Configuration
Array Initialization
Initialization Mode Processing
EVICTENABLE0
14Initialization and Configuration
Internal Processor Register Power-Up Reset State
10 Internal Processor Registers at Power-Up Reset State
External Interface Initialization
Internal Processor Register Power-Up Reset State
Ieee 1149.1 Test Port Reset
Ieee 1149.1 Test Port Reset
Reset State Machine
16Initialization and Configuration
Reset State Machine
11 21264/EV67 Reset State Machine State Descriptions
18Initialization and Configuration
Differential Reference Clocks
Phase-Lock Loop PLL Functional Description
Phase-Lock Loop PLL Functional Description
PLL Output Clocks
Power-Up/Reset Clocking
20Initialization and Configuration
21264/EV67 Error Detection Mechanisms
Error Detection and Error Handling
Error Detection and Error Handling
Dcache Tag Parity Error
Data Error Correction Code
Icache Data or Tag Parity Error
Data Error Correction Code
Dcache Data Single-Bit Correctable ECC Error
Dcache Data Single-Bit Correctable ECC Error
Load Instruction
Dcache Store Second Error
Dcache Store Second Error
Dcache Duplicate Tag Parity Error
Store Instruction Quadword or Smaller
Bcache Tag Parity Error
Bcache Tag Parity Error
Bcache Data Single-Bit Correctable ECC Error
Icache Fill from Bcache
Bcache Victim Read
Bcache Victim Read During a Dcache/Bcache Miss
Icache Fill from Memory
Memory/System Port Single-Bit Data Correctable ECC Error
Memory/System Port Single-Bit Data Correctable ECC Error
Dcache Fill from Memory
Bcache Data Single-Bit Correctable ECC Error on a Probe
Bcache Data Single-Bit Correctable ECC Error on a Probe
Double-Bit Fill Errors
Double-Bit Fill Errors
Error Case Summary
3summarizes the various error cases and their ramifications
Error Case Summary
10Error Detection and Error Handling
Mchk Cstatistreammemdbl
Mchk Cstatdstreambcdbl
Mchk Cstatdstreammemdbl
Page
1lists the maximum electrical ratings for the 21264/EV67
Electrical Characteristics
Electrical Data
Maximum Electrical Ratings
Signal Types
DC Characteristics
DC Characteristics
Idcpower
Input Differential Amplifier Receiver IDA
VDD Idcpower
Input DC Reference Pin Idcref
Input Differential Amplifier Clock Receiver Idaclk
IOZ
Pin Type Open-Drain Driver for Test Pins Oodtp
Pin Type Open-Drain Output Driver OOD
Codtp
11 Push-Pull Output Driver OPP
12 Push-Pull Output Clock Driver Oppclk
AC Characteristics
AC Characteristics
AC Test Conditions
13 AC Specifications
TSU TDH
TSU1 TDH2
AC Characteristics
Page
Operating Temperature at Heat Sink Center Tc
Operating Temperature
Ambient temperature requirement
Thermal Management
Θca at Various Airflows for 21264/EV67
Operating Temperature
10-2Thermal Management
Heat Sink Specifications
Heat Sink Specifications
Type 1 Heat Sink
10-4Thermal Management
Type 2 Heat Sink
Type 3 Heat Sink
10-6Thermal Management
Thermal Design Considerations
Thermal Design Considerations
Page
Dedicated Test Port Pins
Testability and Diagnostics
Test Pins
Testability and Diagnostics
11-2Testability and Diagnostics
SROM/Serial Diagnostic Terminal Port
SROM/Serial Diagnostic Terminal Port
Srom Load Operation
Ieee 1149.1 Port
Ieee 1149.1 Port
Ieee 1149.1 Instructions and Opcodes
TestStatH Pin
11-4Testability and Diagnostics
TestStatH Pin
Built-in Self-Test
Power-Up Self-Test and Initialization
Power-Up Self-Test and Initialization
Srom Initialization
11-6Testability and Diagnostics
Serial Instruction Cache Load Operation
Icache Bit Fields in an Srom Line
See Appendix B for a listing of the Boundary-Scan Register
References
Page
Table A-1 Instruction Format and Opcode Notation
Alpha Instruction Set
Alpha Instruction Summary
Alpha Instruction Set A-1
Alpha Instruction Summary
Opr 11.24 Cmove if = zero
Mbr Branch to subroutine
Pcd Trap to PALcode
Opr 11.46 Cmove if ≥ zero
15.0BC Convert quadword to Ffloating
15.0AF Convert Gfloating to quadword
17.010 Convert longword to quadword
15.0BE Convert quadword to Gfloating
17.02C Fcmove if zero
17.02F Fcmove if zero
17.02E Fcmove if ≤ zero
17.02B Fcmove if ≠ zero
Opr 1C.31 Pixel error
Opr 13.40 Multiply longword with integer overflow enable
Opr 13.60 Multiply quadword with integer overflow enable
Mem Load Sfloating
Mfc 18.C000 Read process cycle counter 18.F000 Read and set
Opr 1C.36 Pack words to bytes Mfc 18.E000 Read and clear
Mbr 1A.2 Return from subroutine
Opr 10.02 Scaled add longword by
Reserved Opcodes
Reserved Opcodes
Opcodes Reserved for Compaq
Ieee Floating-Point Instructions
Ieee Floating-Point Instructions
Independent Floating-Point Instructions
VAX Floating-Point Instructions
VAX Floating-Point Instructions
Opcode Summary
Opcode Summary
Ieee floating-point instruction opcodes
Mem Table A-9explains the symbols used in Table A-8
Mem Res
Floating-point operate instruction opcodes
Ieee Floating-Point Conformance
Ieee Floating-Point Conformance
14Alpha Instruction Set
Table A-11 Exceptional Input and Output Conditions
Alpha Instruction Set A-15
Cmptlt Cmptle Input
Cmpteq Cmptun Input
16Alpha Instruction Set
Fbeq Fbne Fblt Fble Fbgt Fbge LDS LDT STS STT Cpys Cpysn
Alpha Instruction Set A-17
Page
21264/EV67 Boundary-Scan Register
Boundary-Scan Register
Boundary-Scan Register
Pllvdd
21264/EV67 Boundary-Scan Register B-3
421264/EV67 Boundary-Scan Register
21264/EV67 Boundary-Scan Register B-5
621264/EV67 Boundary-Scan Register
21264/EV67 Boundary-Scan Register B-7
821264/EV67 Boundary-Scan Register
21264/EV67 Boundary-Scan Register B-9
1021264/EV67 Boundary-Scan Register
21264/EV67 Boundary-Scan Register B-11
1221264/EV67 Boundary-Scan Register
Serial Icache Load Predecode Values
Serial Icache Load Predecode Values C-1
Page
PALcode Restrictions and Guidelines
PALcode Restrictions and Guidelines D-1
2PALcode Restrictions and Guidelines
PALcode Restrictions and Guidelines D-3
4PALcode Restrictions and Guidelines
PALcode Restrictions and Guidelines D-5
Initwritemany
6PALcode Restrictions and Guidelines
PALcode Restrictions and Guidelines D-7
8PALcode Restrictions and Guidelines
Restriction 7 Replay Trap, Interrupt Code Sequence, and STF
PALcode Restrictions and Guidelines D-9
Restriction 9 PALmode Istream Address Ranges
Restriction 10 Duplicate IPR Mode Bits
Restriction 9 PALmode Istream Address Ranges
10PALcode Restrictions and Guidelines
Restriction 13 DTB Fill Flow Collision
Restriction 11 Ibox IPR Update Synchronization
Restriction 11 Ibox IPR Update Synchronization
Restriction 14 Hwret
Restriction 21 HWRET/STALL After Hwmtpr ASN0/ASN1
Guideline 20 Ictlsbe Stream Buffer Enable
Guideline 16 JSR-BAD VA
Guideline 16 JSR-BAD VA
Restriction 22 HWRET/STALL After Hwmtpr IS0/IS1
Restriction 22 HWRET/STALL After Hwmtpr IS0/IS1
PALcode Restrictions and Guidelines D-13
Restriction 24 HWRET/STALL After Hwmtpr ICFLUSH, Icflushasm
Restriction 25 Hwmtpr Itbia After Reset
Guideline 26 Conditional Branches in PALcode
14PALcode Restrictions and Guidelines
Restriction 30 Hwmtpr and Hwmfpr to the Cbox CSR
Guideline 29 JSR, JMP, RET, and Jsrcor in PALcode
PALcode Restrictions and Guidelines D-15
Restriction 30 Hwmtpr and Hwmfpr to the Cbox CSR
16PALcode Restrictions and Guidelines
Restriction 31 ICTLVA48 Update
Restriction 31 ICTLVA48 Update
Restriction 32 Pctrctl Update
PALcode Restrictions and Guidelines D-17
Restriction 36 Updating Ictlsde
Guideline 35 Hwintclr Update
Restriction 33 Hwld Physical/Lock Use
Restriction 37 Updating VACTLVA48
Restriction 40 Scrubbing a Single-Bit Error
PALcode Restrictions and Guidelines D-19
Restriction 40 Scrubbing a Single-Bit Error
20PALcode Restrictions and Guidelines
Restriction 43 No Trappable Instructions Along with
Restriction 42 Updating VACTL, CCCTL, or CC IPRs
PALcode Restrictions and Guidelines D-21
Restriction 47 Cache Eviction for Single-Bit Cache Errors
22PALcode Restrictions and Guidelines
Restriction 47 Cache Eviction for Single-Bit Cache Errors
PALcode Restrictions and Guidelines D-23
24PALcode Restrictions and Guidelines
Forwarding Clock Pin Groupings
21264/EV67-to-Bcache Pin Interconnections
Table E-1 Bcache Forwarding Clock Pin Groupings
Data Pin Usage
Late-Write Non-Bursting SSRAMs
Late-Write Non-Bursting SSRAMs
Tag Pin Usage
Data and Tag Pin Usage
Dual-Data Rate SSRAMs
Dual-Data Rate SSRAMs
Table E-4 Dual-Data Rate Ssram Data Pin Usage
Trstl
Table E-5 Dual-Data Rate Ssram Tag Pin Usage
Glossary
BIU
BSR
Cisc
CPU
Cmos
CPI
CSR
DTB
DMA
Dram
DTL
FEU
Feprom
FET
Fpga
Gclk
IDU
ITB
Iowb
Ipga
Jfet
MBZ
MAF
MBO
Mips
Nmos
MSI
Naturally Aligned
Nvram
PLA
PAL
PGA
Plcc
RAM
Pqfp
Prom
RAS
RTL
Risc
ROM
SAM
SIP
Sdram
Simm
Sipp
Uart
Stram
TTL
Unaligned
VAF
Unpredictable
Uvprom
VDF
WAR
Writeblock
Index
Numerics
Index-2
Index-3
Index-4
ECC
Index-6
Index-7
Index-8
Index-9
Index-10
Index-11
Index-12
