Compaq EV67, 21264 specifications Ibox Status Register Istat, Spce, 18Internal Processor Registers

Ibox IPRs

Table 5–11 Ibox Control Register Fields Description (Continued)

Name	Extent	Type	Description
SBE[1:0]	[9:8]	RW,0	Stream Buffer Enable.
			The value in this bit field specifies the number of Istream
			buffer prefetches (besides the demand-fill) that are launched
			after an Icache miss. If the value is zero, only demand
			requests are launched.
SDE[1:0]	[7:6]	RW,0	PALshadow Register Enable.
			Enables access to the PALshadow registers. If SDE[1] is set,
			R4-R7 and R20-R23 are used as PALshadow registers.
			SDE[0] does not affect 21264/EV67 operation.
SPE[2:0]	[5:3]	RW,0	Super Page Mode Enable.
			Identical to the SPE bits in the Mbox M_CTL SPE[2:0]. See
			Section 5.3.9.
IC_EN[1:0]	[2:1]	RW,3	Icache Set Enable.
			At least one set must be enabled. The entire cache may be
			enabled by setting both bits. Zero, one, or two Icache sets
			can be enabled.
			This bit does not clear the Icache, but only disables fills to
			the affected set.
SPCE	[0]	RW,0	System Performance Counting Enable.
			Enables performance counting for the entire system if indi-

vidual counters (PCTR0 or PCTR1) are enabled by setting PCT0_EN or PCT1_EN, respectively.

Performance counting for individual processes can be enabled by setting PCTX[PPCE]. See Section 5.2.21 for more information.

See Section 6.10 for information about performance count- ing.

5.2.16 Ibox Status Register – I_STAT

The Ibox status register (I_STAT) is a read/write-1-to-clear register that contains Ibox status information.

Usage of I_STAT in performance monitoring is described in Section 6.10.

Figure 5–23shows the Ibox status register.

5–18Internal Processor Registers Alpha 21264/EV67 Hardware Reference Manual