Compaq EV67, 21264 specifications Victim Data Buffer, Cache Coherency Basics

Victim Data Buffer

•Issuing probes and SysDc fill commands to the 21264/EV67 out-of-order with respect to their order at the system serialization point

•Filtering out all probe misses from the 21264/EV67 cache system

If a probe misses in the 21264/EV67 cache system (Bcache miss and VAF miss), the 21264/EV67 stalls probe processing with the expectation that a SysDc fill will allocate this block. Because of this, in duplicate tag mode, the 21264/EV67 can never generate a probe miss response.

When Cbox CSR DUP_TAG_ENA[0] equals 0, the 21264/EV67 delivers a miss response for probes that do not hit in its cache system.

4.4 Victim Data Buffer

The 21264/EV67 has eight victim data buffers (VDBs). They have the following prop- erties:

•The VDBs are used for both victims (fills that are replacing dirty cache blocks) and for system probes that require data movement. The CleanVictimBlk command (optional) assigns and uses a VDB.

•Each VDB has two valid bits that indicate the buffer is valid for a victim or valid for a probe or valid for both a victim and a probe. Probe commands that match the address of a victim address file (VAF) entry with an asserted probe-valid bit (P) will stall the 21264/EV67 probe queue. No ProbeResponses will be returned until the P bit is clear.

•The release victim buffer (RVB) bit, when asserted, causes the victim valid bit, on the victim data buffer (VDB) specified in the ID field, to be cleared. The RVB bit will also clear the IOWB when systems move data on I/O write transactions. In this case, ID[3] equals one.

•The release probe buffer (RPB) bit, when asserted (with a WriteData or Release- Buffer SysDc command), clears the P bit in the victim buffer entry specified in the ID field.

•Read data commands and victim write commands use IDs 0-7, while IDs 8-11 are used to address the four I/O write buffers.

4.5Cache Coherency

This section describes the basics and protocols of the 21264/EV67 cache coherency scheme.

4.5.1 Cache Coherency Basics

The 21264/EV67 systems maintain the cache hierarchy shown in Figure 4–3.

4–8 Cache and External Interfaces Alpha 21264/EV67 Hardware Reference Manual