Compaq 21264, EV67 Dcache Status Register Dcstat, 20describes the Dcache control register fields

Mbox IPRs

Figure 5–33 Dcache Control Register

63 8 7 6 5 4 3 2 1 0

DCDAT_ERR_EN
DCTAG_PAR_EN
F_BAD_DECC
F_BAD_TPAR
F_HIT
SET_EN[1:0]
					LK99-0041A
	Table 5–20describes the Dcache control register fields.
Table 5–20 Dcache Control Register Fields Description
Name		Extent	Type	Description
Reserved		[63:8]	—	—
DCDAT_ERR_EN		[7]	WO,0	Dcache data ECC and parity error enable.
DCTAG_PAR_EN		[6]	WO,0	Dcache tag parity enable.
F_BAD_DECC		[5]	WO,0	Force Bad Data ECC. When set, ECC data is not written into
				the cache along with the block that is loaded by a fill or store.
				Writing data that is different from that already in the block will
				cause bad ECC to be present. Since the old ECC value will
				remain, the ECC will be bad.
F_BAD_TPAR		[4]	WO,0	Force Bad Tag Parity. When set, this bit causes bad tag parity to
				be put into the Dcache tag array during Dcache fill operations.
Reserved		[3]	—	—
F_HIT		[2]	WO,0	Force Hit. When set, this bit causes all memory space load and
				store instructions to hit in the Dcache, independent of the
				Dcache tag address compare. F_HIT does not force the status of
				the block to register as DIRTY (the tag status bits are still con-
				sulted), so stores may still generate offchip activity.
				In this mode, only one of the two sets may be enabled, and tag
				parity checking must be disabled (set DCTAG_PER_EN to
				zero).
SET_EN[1:0]		[1:0]	WO,3	Dcache Set Enable. At least one set must be enabled.

5.3.11 Dcache Status Register – DC_STAT

The Dcache status register (DC_STAT) is a read-write register. If a Dcache tag parity error or data ECC error occurs, information about the error is latched in this register. Figure 5–34shows the Dcache status register.

Alpha 21264/EV67 Hardware Reference Manual Internal Processor Registers 5–31