Compaq EV67, 21264 specifications WMB Instruction Processing, TB Fill Flow Example Sequence

I/O Write Buffer and the WMB Instruction

Because the MB instruction is executed speculatively, MB processing can begin and the original MB can be killed. In the internal acknowledge case, the MB may have already been sent to the system interface, and the system is still expected to respond to the MB.

2.12.1.2 WMB Instruction Processing

Write memory barrier (WMB) instructions are issued into the Mbox store-queue, where they wait until they are retired and all prior store instructions become writable. The Mbox then stalls the writable pointer and informs the Cbox. The Cbox closes the IOWB merge register and responds in one of the following two ways:

•If Cbox CSR SYSBUS_MB_ENABLE is clear, the Cbox performs the following actions:

a.Stalls further MAF and IOWB processing.

b.Monitors Cbox CSR MB_CNT[3:0], a 4-bit counter of outstanding committed events. When the counter decrements from one to zero, the Cbox marks the youngest probe queue entry.

c.When a probe response has been sent to the system for the marked probe queue entry, the Cbox considers the WMB to be satisfied.

•If Cbox CSR SYSBUS_MB_ENABLE is set, the Cbox performs the following actions:

a.Stalls further MAF and IOWB processing.

b.Sends the MB command to the system port.

c.Waits until the MB command is acknowledged by the system with a SysDc MBDone command, then sends acknowledge and marks the youngest entry in the probe queue.

d.When a probe response has been sent to the system for the marked probe queue entry, the Cbox considers the WMB to be satisfied.

2.12.1.3TB Fill Flow

Load instructions (HW_LDs) to a virtual page table entry (VPTE) are processed by the 21264/EV67 to avoid litmus test problems associated with the ordering of memory transactions from another processor against loading of a page table entry and the subse- quent virtual-mode load from this processor.

Consider the sequence shown in Table 2–12.The data could be in the Bcache. Pj should fetch datai if it is using PTEi.

Table 2–12 TB Fill Flow Example Sequence 1

Pi	Pj
Write Datai	Load/Store datai
MB	<TB miss>
Write PTEi	Load-PTE
	<write TB>
	Load/Store (restart)

2–34Internal Architecture Alpha 21264/EV67 Hardware Reference Manual