Compaq 21264, EV67 3.3 Pin Assignments

3–8 Hardware Interface

Alpha 21264/EV67 Hardware Reference Manual

Pin Assignments

3.3 Pin Assignments

The 21264/EV67 package has 587 pins aligned in a pin grid array (PGA) design. There

are 380 functional signal pins, 1 dedicated 3.3-V pin for the PLL, 112 ground VSS pins,

and 94 VDD pins. Table 3–4 lists the signal pins an d thei r corr espondi ng p in grid ar ray

(PGA) locations in alphabetical order for the signal type. Table 3–5 lists the pin grid

array locations in alphabetical order

Reset_L I_DA 1 System reset. This signal protects the 21264/EV67 from dam-

age during initial power-up. It must be asserted until

DCOK_H is asserted. After that, it is deasserted and the

21264/EV67 begins its reset sequence.

SromClk_H O_OD_TP 1 Serial ROM clock.

SromData_H I_DA 1 Serial ROM data.

SromOE_L O_OD_TP 1 Serial ROM enable.

Tck_ H I_DA 1 IEEE 1149.1 test clock.

Tdi_H I_DA 1 IEEE 1149.1 test data-in signal.

Tdo_H O_OD_TP 1 IEEE 1149.1 test data-out signal.

Test Stat _H O_OD_TP 1 Test status pin.

Tms_H I_DA 1 IEEE 1149.1 test mode select signal.

Trst_ L I_DA 1 IEEE 1149.1 test access port (TAP) reset signal.

Table 3–4 Pin List Sorted by Signal N ame

Signal Name PGA Location Signal Name PGA Location Signal Name PGA Location

BcAdd_H_10 B30 BcAdd_H_11 D30 BcAdd_H_12 C31

BcAdd_H_13 H28 BcAdd_H_14 G29 BcAdd_H_15 A33

BcAdd_H_16 E31 BcAdd_H_17 D32 BcAdd_H_18 B34

BcAdd_H_19 A35 BcAdd_H_20 B36 BcAdd_H_21 H30

BcAdd_H_22 C35 BcAdd_H_23 E33 BcAdd_H_4 B28

BcAdd_H_5 E27 BcAdd_H_6 A29 BcAdd_H_7 G27

BcAdd_H_8 C29 BcAdd_H_9 F28 BcCheck_H_0 F2

BcCheck_H_1 AB4 BcCheck_H_10 AW1 BcCheck_H_11 BD10

BcCheck_H_12 E45 BcCheck_H_13 AC45 BcCheck_H_14 AT4 4

BcCheck_H_15 BB36 BcCheck_H_2 AT2 BcCheck_H_3 BC11

BcCheck_H_4 M38 BcCheck_H_5 AB42 BcCheck_H_6 AU43

BcCheck_H_7 BC37 BcCheck_H_8 M8 BcCheck_H_9 AA3

BcData_H_0 B10 BcData_H_1 D10 BcData_H_10 L3

BcData_H_100 D42 BcData_H_101 D44 BcData_H_102 H40

BcData_H_103 H42 BcData_H_104 G45 BcData_H_105 L43

Table 3–3 21264/EV67 Signal Descriptions by Function (Continued)

Signal Type Count Description

Contents

Main Alpha 21264/EV67 Hardware Reference Manual Table of Contents Preface 1 Introduction 2 Internal Architecture Alpha 21264/EV67 Hardware Reference Manual 3 Hardware Interface 4 Cache and External Interfaces 5 Internal Processor Registers Alpha 21264/EV67 Hardware Reference Manual 6 Privileged Architecture Library Code Alpha 21264/EV67 Hardware Reference Manual 7 Initialization and Configuration 8 Error Detection and Error Handling 9 Electrical Data 10 Thermal Management 11 Testability and Diagnostics A Alpha Instruction Set B 21264/EV67 Boundary-Scan Register C Serial Icache Load Predecode Values D PALcode Restrictions and Guidelines E 21264/EV67-to-Bcache Pin Interconnections Glossary Index Figures Alpha 21264/EV67 Hardware Reference Manual Tables Page Page Page Preface Audience Content Page Terminology and Conventions Page A capital X represents any valid value. Page Page Page Introduction 1.1 The Architecture The Architecture 1.1.1 Addressing 1.1.2 Integer Data Types 1.1.3 Floating-Point Data Types 1.2 21264/EV67 Microprocessor Features Page Internal Architecture 2.1 21264/EV67 Microarchitecture Page Internal Architecture Figure 21 21264/EV67 Block Diagram 2.1.1.2 Branch Predictor Page Page Page Page 2.1.2 Integer Execution Unit Page Page Page Page 2.1.7 SROM Interface 2.2 Pipeline Or ganization Page Page 2.2.1 Pipeline Aborts 2.3 Instruction Issue Rules 2.3.1 Instruction Group Definitions 2.3.2 Ebox Slotting Page 2.3.3 Instruction Latencies Instruction Retire Rules 2.4 Instruction Retire Rules 2.5 Retire of Operate Instructions into R31/F31 Load Instructions to R31 and F31 2.6 Load Instructions to R31 and F31 2.6.1 Normal Prefetch: LDBU, LDF, LDG, LDL, LDT, LDWU, HW_LDL Instructions 2.6.2 Prefetch with Modify Intent: LDS Instruction 2.6.3 Prefetch, Evict Next: LDQ and HW_LDQ Instructions 2.6.4 Prefetch with the LDx_L / STx_C Instruction Sequence 2.7 Special Cases of Alpha Instruction Execution 2.7.1 Load Hit Speculation Page 2.7.2 Floating-Point Store Instructions 2.7.3 CMOV Instruction 2.8 Memory and I/O Address Space Instructions 2.8.1 Memory Address Space Load Instructions 2.8.2 I/O Address Space Load Instructions 2.8.3 Memory Address Space Store Instructions 2.8.4 I/O Address Space Store Instructions MAF Memory Address Space Merging Rules 2.9 MAF Memory Address Space Merging Rules 2.10 Instruction Ordering Replay Traps 2.11 Replay Traps 2.11.1 Mbox Order Traps 2.11.2 Other Mbox Replay Traps 2.12 I/O Write Buffer and the WMB Instruction 2.12.1 Memory Barrier (MB/WMB/TB Fill Flow) Page Page Performance Measurement SupportPerformance Counters 2.13 Performance Measurement SupportPerformance Counters 2.14 Floating-Point Control Register Floating-Point Control Register AMASK and IMPLVER Instruction Values 2.15 AMASK and IMPLVER Instruction Values For the 21264/EV67, the IMPLVER instruction returns the value 2. 2.15.1 AMASK 2.15.2 IMPLVER Design Examples 2.16 Design Examples 240 Internal Architecture Design Examples Figure 213 Typical Multiprocessor Configuration Hardware Interface 3.1 21264/EV67 Microprocessor Logic Symbol 32 Hardware Interface 21264/EV67 Microprocessor Logic Symbol Figure 31 21264/EV67 Microprocessor Logic Symbol x 3.2 21264/EV67 Signal Names and Functions Table 31 defines the 21264/EV67 signal types referred to in this section. Page Page Table 33 lists signals by function and provides an abbreviated description. Page 3.3 Pin Assignments Page Page Hardware Interface Table 35 Pin List Sorted by PGA Location Table 34 Pin List Sorted by Signal Name (Continued) Hardware Interface Table 35 Pin List Sorted by PGA Location (Continued) Table 35 P in List Sorted by PGA Location (Continued) Hardware Interface Table 35 Pin List Sorted by PGA Location (Continued) Table 36 lists the 21264/EV67 ground and power (VSS and VDD, respectively) pin list. Table 36 Ground and Power (VSS and VDD) Pin List Hardware Interface Mechanical Specifications 3.4 Mechanical Specifications Figure 32 Package Dimensions 318 Hardware Interface 21264/EV67 Packaging 21264/ 3.5 21264/EV67 Packaging Figure 33 shows the 21264/EV67 pinout from the top view with pins facing down. Figure 33 21264/EV67 Top View (Pin Down) 67 View 21264/EV67 Packaging 21264/ Figure 34 shows the 21264/EV67 pinout from the bottom view with pins facing up. Figure 34 21264/EV67 Bottom View (Pin Up) 67 Page Cache and External Interfaces 4.1 Introduction to the External Interfaces Introduction to the External Interfaces Cache and External Interfaces Introduction to the External Interfaces x Figure 41 21264/EV67 System and Bcache Interfaces 4.1.1 System Interface x 4.2 Physical Address Considerations Page Page Bcache Structure 4.3 Bcache Structure 4.3.1 Bcache Interface Signals 4.3.2 System Duplicate Tag Stores 4.4 Victim Data Buffer 4.5 Cache Coherency Page 4.5.3 Cache Block State Transitions Page Page 4.5.5 Dcache States and Duplicate Tags Lock Mechanism 4.6 Lock Mechanism Lock Mechanism 4.6.1 In-Order Processing of LDx_L/STx_C Instructions 4.6.2 Internal Eviction of LDx_L Blocks 4.6.3 Liveness and Fairness 4.6.4 Managing Speculative Store Issues with Multiprocessor Systems 4.7 System Port 4.7.1 System Port Pins 4.7.2 Programming the System Interface Clocks 4.7.3 21264/EV67-to-System Commands Table 411 shows the command format for page hit mode (21264/EV67-to-system). Table 412 describes the field definitions for Tables 410 and 411. 4.7.4 21264/EV67-to-System Commands Descriptions Page Page 4.7.5 ProbeResponse Commands (Command[4:0] = 00001) 4.7.6 SysAck and 21264/EV67-to-System Commands Flow Control 4.7.7 System-to-21264/EV67 Commands Table 420 describes the system-to-21264/EV67 probe commands fields descriptions. Table 422 lists the next cache block state selected by Probe[2:0]. Page Page 4.7.8 Data Movement In and Out of the 21264/EV67 Page Page Page Page Page Page 4.7.9 Nonexistent Memory Processing Table 432 shows each 21264/EV67 command, with NXM addresses, and the appropri- ate system response. Page 21264/EV67 fails the STx_C instruction as defined in the Alpha Architecture Handbook, Version 4 because the 21264/EV67 does not yet own the block. 4.8 Bcache Port 4.8.1 Bcache Port Pins 4.8.2 Bcache Clocking Page Page 4.8.3 Bcache Transactions Page Page 4.8.4 Pin Descriptions Page Page Interrupts 4.8.5 Bcache Banking 4.8.6 Disabling the Bcache for Debugging 4.9 Interrupts Internal Processor Registers Mbox IPRs Table 51 Internal Processor Registers (Continued) 5.1 Ebox IPRs 5.1.1 Cycle Counter Register CC 5.1.2 Cycle Counter Control Register CC_CTL 5.1.3 Virtual Address Register VA 5.1.4 Virtual Address Control Register VA_CTL 5.1.5 Virtual Address Format Register VA_FORM 5.2 Ibox IPRs 5.2.1 ITB Tag Array Write Register ITB_TAG 5.2.2 ITB PTE Array Write Register ITB_PTE 5.2.3 ITB Invalidate All Process (ASM=0) Register ITB_IAP 5.2.4 ITB Invalidate All Register ITB_IA 5.2.5 ITB Invalidate Single Register ITB_IS 5.2.6 ProfileMe PC Register PMPC 5.2.7 Exception Address Register EXC_ADDR 5.2.8 Instruction Virtual Address Format Register IVA_FORM 5.2.9 Interrupt Enable and Current Processor Mode Register IER_CM Table 55 describes the interrupt enable and current processor mode register fields. 5.2.10 Software Interrupt Request Register SIRR 5.2.11 Interrupt Summary Register ISUM Table 57 describes the interrupt summary register fields. 5.2.12 Hardware Interrupt Clear Register HW_INT_CLR 5.2.13 Exception Summary Register EXC_SUM Table 59 describes the exception summary register fields. 5.2.14 PAL Base Register PAL_BASE 5.2.15 Ibox Control Register I_CTL Table 511 describes the Ibox control register fields. Page 5.2.16 Ibox Status Register I_STAT Table 512 describes the Ibox status register fields. Page 5.2.17 Icache Flush Register IC_FLUSH 5.2.18 Icache Flush ASM Register IC_FLUSH_ASM 5.2.19 Clear Virtual-to-Physical Map Register CLR_MAP 5.2.20 Sleep Mode Register SLEEP 5.2.21 Process Context Register PCTX Table 514 describes the process context register fields. 5.2.22 Performance Counter Control Register PCTR_CTL Table 515 describes the performance counter control register fields. 5.3 Mbox IPRs 5.3.1 DTB Tag Array Write Registers 0 and 1 DTB_TAG0, DTB_TAG1 5.3.2 DTB PTE Array Write Registers 0 and 1 DTB_PTE0, DTB_PTE1 5.3.3 DTB Alternate Processor Mode Register DTB_ALTMODE 5.3.4 Dstream TB Invalidate All Process (ASM=0) Register DTB_IAP 5.3.5 Dstream TB Invalidate All Register DTB_IA 5.3.6 Dstream TB Invalidate Single Registers 0 and 1 DTB_IS0,1 5.3.7 Dstream TB Address Space Number Registers 0 and 1 DTB_ASN0,1 5.3.8 Memory Management Status Register MM_STAT the Ibox EXC_SUM register. 5.3.9 Mbox Control Register M_CTL Table 519 describes the Mbox control register fields. erences to superpages result in access violations. 5.3.10 Dcache Control Register DC_CTL Table 520 describes the Dcache control register fields. 5.3.11 Dcache Status Register DC_STAT 5.4 Cbox CSRs and IPRs 5.4.1 Cbox Data Register C_DATA Figure 535 shows the Cbox data register. Table 522 describes the Cbox data register fields. 5.4.2 Cbox Shift Register C_SHFT Figure 536 shows the Cbox shift register. Page Page Page 5.4.4 Cbox WRITE_MANY Chain Description The WRITE_MANY chain order is contained in Table 525. Note the following: chain. are indicated in italics and have two leading asterisks. CSRs is contained in Chapter 3. Table 525 describes the Cbox WRITE_MANY chain order from LSB to MSB. Figure 537 shows an example of PALcode used to write to the WRITE_MANY chain. Page 5.4.5 Cbox Read Register (IPR) Description The Cbox read register is read 6 bits at a time. Table 526 show s the orde ring fr om LSB to MSB. Page Privileged Architecture Library Code 6.1 PALcode Description PALmode Environment 6.2 PALmode Environment Required PALcode Function Codes 6.3 Required PALcode F unction Codes 6.4 Opcodes Reserved for PALcode 6.4.1 HW_LD Instruction Table 63 describes the HW_LD instruction fields. 6.4.2 HW_ST Instruction 6.4.3 HW_RET Instruction Table 65 describes the HW_RET instruction fields. 6.4.4 HW_MFPR and HW_MTPR Instructions 6.5 Internal Processor Register Access Mechanisms 6.5.1 IPR Scoreboard Bits 6.5.2 Hardware Structure of Explicitly Written IPRs 6.5.3 Hardware Structure of Implicitly Written IPRs 6.5.4 IPR Access Ordering 6.5.5 Correct Ordering of Explicit Writers Followed by Implicit Readers PALshadow Registers 6.5.6 Correct Ordering of Explicit Readers Followed by Implicit Writers 6.6 PALshadow Registers 6.7 PALcode Emulation of the FPCR PALcode Entry Points 6.7.1 Status Flags 6.7.2 MF_FPCR 6.8 PALcode Entry Points 6.8.1 CALL_PAL Entry Points PALcode Entry Points 6.8.2 PALcode Exception Entry Points 6.9 Translation Buffer (TB) Fill Flows 6.9.1 DTB Fill Figure 65 shows single-miss DTB instructions flow. Figure 65 shows single-miss DTB instructions flow. 6.10 Performance Counter Support 6.10.1 General Precautions 6.10.2 Aggregate Mode Programming Guidelines Page E 6.10.3 ProfileMe Mode Programming Guidelines Page Page E Table 614 shows the counter modes that are used with ProfileMe mode. Initialization and Configuration 7.1 Power-Up Reset Flow and the Reset_L and DCOK_H Pins Page 7.1.1 Power Sequencing and Reset State for Signal Pins 7.1.2 Clock Forwarding and System Clock Ratio Configuration Page 7.1.3 PLL Ramp Up 7.1.4 BiST and SROM Load and the TestStat_H Pin 7.1.5 Clock Forward Reset and System Interface Initialization Fault Reset Flow 7.2 Fault Reset Flow Energy Star Certification and Sleep Mode Flow 7.3 Energy Star Certification and Sleep Mode Flow Energy Star Certification and Sleep Mode Flow Warm Reset Flow Table 77 describes each signal and constraint for the sleep mode sequence. 7.4 Warm Reset Flow Array Initialization 7.5 Array Initialization 7.6 Initialization Mode Processing Initialization Mode Processing External Interface Initialization 7.7 External Interface Initialization 7.8 Internal Processor Register Power-Up Reset State Internal Processor Register Power-Up Reset State IEEE 1149.1 Test Port Reset 7.9 IEEE 1149.1 Test Port Reset 7.10 Reset State Machine Initialization and Configuration Reset State Machine Figure 75 21264/EV67 Reset State Machine State Diagram Table 711 21264/EV67 Reset State Machine State Descriptions State Name Description Page Phase-Lock Loop (PLL) Functional Description 7.11 Phase-Lock Loop (PLL) Functional Description 7.11.1 Differential Reference Clocks 7.11.2 PLL Output Clocks Phase-Lock Loop (PLL) Functional Description Error Detection and Error Handling Data Error Correction Code 8.1 Data Error Correction Code 8.2 Icache Data or Tag Parity Error 8.3 Dcache Tag Parity Error 8.4 Dcache Data Single-Bit Correctable ECC Error 8.5 Dcache Store Second Error 8.6 Dcache Duplicate Tag Parity Error 8.7 Bcache Tag Parity Error 8.8 Bcache Data Single-Bit Correctable ECC Error Page 8.9 Memory/System Port Single-Bit Data Correctable ECC Error 8.10 Bcache Data Single-Bit Correctable ECC Error on a Probe Double-Bit Fill Errors 8.11 Double-Bit Fill Errors 8.12 Error Case Summary Page Error Case Summary Page Electrical Data 9.1 Electrical Characteristics 9.2 DC Characteristics symbol indicates current flowing into a 21264/EV67 pin. Page Power Supply Sequencing and Avoiding Potential Failure Mechanisms 9.3 Power Supply Sequencing and Avoiding Potential Failure Mech- anisms 9.4 AC Characteristics Electrical Data Table 913 AC Specifications 98 Electrical Data chain (Table 524) is set to zero phases of delay between forwarded clock out and address/data. BcTagOutClkl_x and BcDataOutClk_x have no programmed offset. Table 913 AC Specifications (Continued) Page Page Thermal Management 10.1 Operating Temperature Operating Temperature 10.2 Heat Sink Specifications Page Thermal Management Figure 102 shows the heat sink type 2, along with its approximate dimensions. Figure 102 Type 2 Heat Sink 106 Thermal Management Figure 103 Type 3 Heat Sink 10.3 Thermal Design Considerations Page Testability and Diagnostics 11.1 Test Pins 11.2 SROM/Serial Diagnostic Terminal Port IEEE 1149.1 Port 11.3 IEEE 1149.1 Port 114 Testability and Diagnostics TestStat_H Pin Scan SequenceScan Sequence Figure 111 TAP Controller State Machine 11.4 TestStat_H Pin Note: A system designer may sample the TestStat_H pin on the first rising edge Power-Up Self-Test and Initialization 11.5 Power-Up Self-Test and Initialization 11.5.1 Built-in Self-Test 11.5.2 SROM Initialization Power-Up Self-Test and Initialization Notes on IEEE 1149.1 Operation and Compliance 11.6 Notes on IEEE 1149.1 Operation and Compliance Page A Alpha Instruction Set A.1 Alpha Instruction Summary Page Page Page Page Page Page Reserved Opcodes A.2 Reserved Opcodes A.2.1 Opcodes Reserved for Compaq IEEE Floating-Point Instructions A.2.2 Opcodes Reserved for PALcode A.3 IEEE Floating-Point Instructions IEEE Floating-Point Instructions VAX Floating-Point Instructions A.4 VAX Floating-Point Instructions A.5 Independent Floating-Point Instructions Opcode Summary A.6 Opcode Summary Required PALcode Function Codes A.7 Required PALcode Function Codes A.8 IEEE Floating-Point Conformance Page See Section 2.14 for information about the floating-point control register (FPCR). Page 21264/EV67 Boundary-Scan Register B 21264/EV67 Boundary-Scan Register This appendix contains the BSDL description of the 21264/EV67 boundary-scan regis- ter. B.1 Boundary-Scan Register B.1.1 BSDL Description of the Alpha 21264/EV67 Boundary-Scan Register B2 21264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B4 21264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B6 21264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B8 21264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B10 21264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B12 21264/EV67 Boundary-Scan Register Page Page PALcode Restrictions and Guidelines D PALcode Restrictions and Guidelines D.1 Restriction 1 : Reset Sequence Required by Retire Logic and Mapper Page Page Page Page Page PALcode Restrictions and Guidelines Restriction 2 : No Multiple Writers to IPRs in Same Scoreboard Group D.2 Restriction 2 : No Multiple Writers to IPRs in S ame Scoreboard Group D.3 Restriction 4 : No Writers and Readers to IPRs in Same Score- board Group Guideline 6 : Avoid Consecutive Read-Modify-Write-Read-Modify-Write D.4 Guideline 6 : Avoid Consecutive Read-Modify-Write-Read- Modify-Write D.5 Restriction 7 : Replay Trap, Interrupt Code Sequence, and STF/ ITOF Restriction 9 : PALmode Istream Address Ranges D.6 Restriction 9 : PALmode Istream Address Ranges D.7 Restriction 10: Duplicate IPR Mode Bits Restriction 11: Ibox IPR Update Synchronization D.8 Restriction 11: Ibox IPR Update Synchronization D.9 Restriction 12: MFPR of Implicitly-Written IPRs EXC_ADDR, IVA_FORM, and EXC_SUM D.10 Restriction 13 : DTB Fill Flow Collision D.11 Restriction 14 : HW_RET Page Restriction 22: HW_RET/STALL After HW_MTPR IS0/IS1 D.18 Restriction 22: HW_RET/STALL After HW_MTPR IS0/IS1 D.19 Restriction 23: HW_ST/P/CONDITIONAL Does Not Clear the Lock Flag Restriction 24: HW_RET/STALL After HW_MTPR IC_FLUSH, IC_FLUSH_ASM, D.20 Restriction 24: HW_RET/STALL After HW_MTPR IC_FLUSH, IC_FLUSH_ASM, CLEAR_MAP D.21 Restriction 25: HW_MTPR ITB_IA After Reset D.22 Guideline 26: Conditional Branches in PALcode Restriction 27: Reset of Force-Fail Lock Flag State in PALcode D.23 Restriction 27: Reset of Force-Fail Lock Flag State in PALcode D.25 Guideline 29 : JSR, JMP, RET, and JSR_COR in PALcode D.26 Restriction 30 : HW_MTPR and HW_MFPR to the Cbox CSR Restriction 30 : HW_MTPR and HW_MFPR to the Cbox CSR Restriction 31 : I_CTL[VA_48] Update D.27 Restriction 31 : I_CTL[VA_48] Update D.28 Restriction 32 : PCTR_CTL Update Restriction 33 : HW_LD Physical/Lock Use D.29 Restriction 33 : HW_LD Physical/Lock Use D.30 Restriction 34 : Writing Multiple ITB Entries in the Same PAL- code Flow D.31 Guideline 35 : HW_INT_CLR Update D.32 Restriction 36 : Updating I_CTL[SDE] D.33 Restriction 37 : Updating VA_CTL[VA_48] D.35 Guideline 39: Writing Multiple DTB Entries in the Same PAL Flow D.36 Restriction 40: Scrubbing a Single-Bit Error Restriction 40: Scrubbing a Single-Bit Error Page Restriction 46: Avoiding Live locks in Speculative Load CRD Handlers D.42 Restriction 46: Avoiding Live locks in Speculative Load CRD Handlers D.43 Restriction 47: Cache Eviction for Single-Bit Cache Errors PALcode Restrictions and Guidelines Restriction 47: Cache Eviction for Single-Bit Cache Errors Page E 21264/EV67-to-Bcache Pin Interconnections This appendix provides the pin interface between the 21264/EV67 and Bcache SSRAMs. E.1 Forwarding Clock Pin Groupings Late-Write Non-Bursting SSRAMs E.2 Late-Write Non-Bursting SSRAMs Unused Bcache tag pins should be pulled to ground through a 200-ohm resistor. Data Pin Usage Tag Pin Usage Dual-Data Rate SSRAMs E.3 Dual-Data Rate SSRAMs Data and Tag Pin Usage Dual-Data Rate SSRAMs Glossary Page Page Page Page Page Page nn Page Page Page Page Page Page Page Page Page Page Index Numerics A B C D E F G H I Page J L M N O P R S T U V W X