Mocomtech CIM-550 6.3.3.2.1Buffer Disabled, 6.3.3.2.2 Buffer Enabled, RX=TX, 6.3.3.2.3 Buffer Enabled, RX<>TX

CiM-550 IP Enabled Satellite Modem	Rev. 2
Theory of Operation	CD/CIM550.IOM

6.3.3.2RECEIVE CLOCKING

There are three receive clocking modes in the CiM-550.

6.3.3.2.1Buffer Disabled

When the buffer is disabled, the receive clock (Receive Timing, or RT) is derived directly from the demodulator, and hence will be subject to plesiochronous and Doppler offsets. In certain instances, this may be acceptable, and in the case of Loop Timing, it is essential that the buffer is disabled (which is done automatically).

6.3.3.2.2 Buffer Enabled, RX=TX

In this instance, it is required that buffer be enabled, so that the clock and data appearing on Receive Timing and Receive Data (RT and RD respectively) are synchronous with the transmit clock. This is a relatively simple case, as the output clock for the buffer is derived directly from either ST or TT.

6.3.3.2.3 Buffer Enabled, RX<>TX

This is an uncommon case, where the receive and transmit data rates are not equal. The modem will generate a phase-locked buffer output clock which uses the transmit clock, regardless of its frequency in relation to the receive data rate.

6.3.3.3 X.21 NOTES

For X.21 operation, use the EIA-422/530 pins, but ignore Receive Clock if the Modem is DTE, and ignore Transmit clocks if the Modem is DCE.

6.3.3.4LOOP TIMING WITH SYNC EIA-232

The CiM-550 distinguishes between synchronous and asynchronous EIA-232 by detecting clock activity on the TX Clock pin of the interface. If no clock is detected, it is assumed that the mode is asynchronous. Therefore, if loop timing is employed in a synchronous EIA-232 application, it is essential to provide an external loop between the ST and TX clock pins. If this is not done, the modem will assume an async mode, which is not compatible. The loop should be placed between pin 15 and pin 24 on the 25 pin ‘D’ type interface.

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