Motorola IH5 manual Block Diagram, 1is a block diagram of the MCPN750A’s overall architecture

Block Diagram

The MCPN750A interfaces to a CompactPCI bus using a DEC 21554 non- transparent PCI-to-PCI bridge device. This device provides a 64-bit primary and a 64-bit secondary interface allowing full 64-bit data access between CompactPCI bus devices and the host/PCI bridge. The non- transparent characteristics of this bridge allows the local MCPN750A processor to configure and control the local MCPN750A resources independently from the system host processor.

Front panel connectors on the MCPN750A include an RJ45 connector for 10BaseT/100BaseTX Ethernet, and an RJ45 connector for the asynchronous serial debug port, COM1. Three additional serial ports, two USB ports, and the one EIDE channel are routed to J3 and J5 for transition module I/O.

Another key feature of the MCPN750A family is the PCI (Peripheral Component Interconnect) bus. In addition to the on-board local bus peripherals, the PCI bus supports an industry-standard mezzanine interface, IEEE P1386.1 PMC (PCI Mezzanine Card), either two single- wide or one double-wide. These PMC slots are 32/64-bit capable and support both front and rear I/O. PMC I/O pins 1 through 64 of each PMC slot are routed to the J3 and J5 connectors for transition module I/O.

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Block Diagram

Figure 6-1is a block diagram of the MCPN750A’s overall architecture.

http://www.motorola.com/computer/literature 6-3