Motorola MCPN750A, IH5 manual Dram Parity Enable On-Detection/Always/Never O/A/N = O?

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CNFG and ENV Commands

allowable ROMNAL setting is $0; the highest allowable is $F. The value to enter depends on processor speed; refer to your Processor/Memory Mezzanine Module User’s Manual for appropriate values. The default value varies according to the system’s bus clock speed.

Note ROM Next Access Length is not applicable to the MCPN750. The configured value is ignored by PPCBug.

DRAM Parity Enable [On-Detection/Always/Never - O/A/N] = O?

ODRAM parity is enabled upon detection. (Default)

ADRAM parity is always enabled.

NDRAM parity is never enabled

Note This parameter (above) also applies to enabling ECC for DRAM.

L2 Cache Parity Enable [On-Detection/Always/Never - O/A/N] = O?

OL2 Cache parity is enabled upon detection. (Default)

AL2 Cache parity is always enabled.

NL2 Cache parity is never enabled

PCI Interrupts Route Control Registers (PIRQ0/1/2/3) = 0A050900?

Initializes the PIRQx (PCI Interrupts) route control registers in the IBC (PCI/ISA bus bridge controller). The ENV parameter is a 32-bit value that is divided by 4 to yield the values for route control registers PIRQ0/1/2/3. The default is determined by system type. For details on PCI/ISA interrupt assignments and for suggested values to enter for this parameter, refer to the 8259 Interrupts section of Chapter 4 in the MCPN750A CompactPCI Single Board Computer Programmer’s Reference Guide.

Serial Startup Code Master Enable [Y/N]=N?

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