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Motorola MCPN750A, IH5 manual Default = $00

Models: IH5 MCPN750A

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CNFG and ENV Commands

Auto Boot Scan Enable [Y/N] = Y?

YIf Autoboot is enabled, the Autoboot process attempts to boot from devices specified in the scan list (e.g.,

FDISK/CDROM/TAPE/HDISK). (Default)

NIf Autoboot is enabled, the Autoboot process uses the Controller LUN and Device LUN to boot.

Auto Boot Scan Device Type List = FDISK/CDROM/TAPE/HDISK?

This is the listing of boot devices displayed if the Autoboot Scan option is enabled. If you modify the list, follow the format shown above (uppercase letters, using forward slash as separator).

Auto Boot Controller LUN = 00?

Refer to the PPCBug Firmware Package User’s Manual for a listing of disk/tape controller modules currently supported by PPCBug. (Default = $00)

Auto Boot Device LUN

= 00?

Refer to the PPCBug Firmware Package User’s Manual for a listing of disk/tape devices currently supported by PPCBug.

(Default = $00)

Auto Boot Partition Number = 00?

Which disk “partition” is to be booted, as specified in the PowerPC Reference Platform (PRP) specification. If set to zero, the firmware will search the partitions in order (1, 2, 3, 4) until it finds the first “bootable” partition. That is then the partition that will be booted. Other acceptable values are 1, 2, 3, or 4. In these four cases, the partition specified will be booted without searching.

Auto Boot Abort Delay = 7?

The time in seconds that the Autoboot sequence will delay before starting the boot. The purpose for the delay is to allow you the option of stopping the boot by use of the BREAK key. The time value is from 0-255 seconds. (Default = 7 seconds)

Auto Boot Default String [NULL for an empty string] =?

4-6	Computer Group Literature Center Web Site

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Motorola MCPN750A, IH5 manual Default = $00

Contents

Installation and Use MCPN750A CompactPCI Single Board ComputerMCPN750A/IH5 September 2001 EditionCopyright 2001 Motorola, Inc All Rights Reserved Printed in the United States of AmericaSafety Summary Use Caution When Exposing or Handling a CRTGround the Instrument Do Not Operate in an Explosive AtmosphereLithium Battery Caution FlammabilityEMI Caution instructionsCE Notice European Community Limited and Restricted Rights Legend Contents CHAPTER 1 Hardware Preparation and InstallationAbout This Manual CHAPTER 2 Startup and Operation CHAPTER 3 PPCBugCHAPTER 4 CNFG and ENV Commands CHAPTER 5 Remote Start Via the PCI BusCHAPTER 6 Functional Description CHAPTER 7 Connector Pin Assignments Specifications APPENDIX AAPPENDIX B Related DocumentationPage List of Figures Page List of Tables Table 7-25. PMC I/O Modules 1 and 2 PIM1 and PIM2 About This Manual Currently, the boards are provided in the following configurationsOverview of Contents Summary of ChangesDate ChangesComments and Suggestions Conventions Used in This Manual boldEnter, Return or CR CTRLHardware Preparation and Installation Block DiagramIntroduction Product DescriptionFigure 1-1. MCPN750A Baseboard Block Diagram Debug Connector33MHz 32/64-bit PCI Local Bus 33MHz 32/64-bit CompactPCI BusOverview of Start-up Procedure Getting StartedTable 1-1. Startup Overview Equipment Required Table 1-1. Startup Overview ContinuedESD Precautions Unpacking InstructionsHardware Configuration PreparationMCPN750A Baseboard Preparation Flash Bank Selection J7 PreparationStand-Alone Operating Mode J8 LEDs Fuses,Connectors,Headers,MCPN750AFigure 1-2.Switches2703 System Considerations TMCPN710 Transition Module Preparation Figure 1-3. TMCPN710 Connector and Header Locations Hardware Preparation and Installation1-12 Computer Group Literature Center Web SiteSerial Ports 1 and Figure 1-4. MCPN750A/TMCPN710 Serial Ports 1 and MCPN750ARJ45 TMCPN710COM3 and COM4 Asynchronous Serial Ports Figure 1-5. TMCPN710 Serial Ports 3 andMCPN750A TMCPN710TM-PIMC-0001 Transition Module Preparation Connector and Header Locations Figure 1-6. TM-PIMC-00012694 COM1 and COM2 Asynchronous Serial Ports Figure 1-7. MCPN750A/TM-PIMC-0001 Serial Ports 1 and MCPN750TM-PIMC-0001 RJ45Figure 1-8. TM-PIMC-0001 Serial Ports 3 and The signals for COM3 and COM4 serial ports are routed to 10-pin headers on the TM-PIMC-0001 Transition Module J12 and J13. These headers function as I/O connectors for the MCPN750A and are permanently configured as DTE. Figure 1-8 depicts this configurationCOM3 and COM4 Asynchronous Serial Ports Hardware Installation Installing PMC Modules on the MCPN750A SBCFigure 1-9. PMC Module Placement on MCPN750A 5. Remove the PMC filler from the front panel of the MCPN750A Installing the MCPN750A Baseboard Hardware Installation Installing a TMCPN710 or TM-PIMC-0001 Transition Module Installing PIMs on the TM-PIMC-0001 Transition ModuleFigure 1-10. Installing a PIM on the TM-PIMC-0001 Transition Module Installing the Transition Module in the Chassis Dangerous voltages, capable of causing death, are present in Figure 1-11. TMCPN710 or TM-PIMC-0001/MCPN750A Mating Configuration Hardware Preparation and Installation1-30 Computer Group Literature Center Web SiteMCPN750A Module Power Requirements VoltageCurrent Available to PMCs & Transition Modules Hardware Preparation and Installation 1-32Computer Group Literature Center Web Site Applying Power Startup and OperationIntroduction Figure 2-1. PPCBug System Startup IF ENABLED AUTOBOOT IF ENABLED OPERATING SYSTEMSTARTUP SYSTEM INITIALIZATION CONSOLE DETECTION RUN SELFTESTS Default Processor Memory Map Table 2-1. Processor Default View of the Memory MapMemory Maps Processor Memory MapTable 2-1. Processor Default View of the Memory Map Continued PCI Local Bus Memory MapCompactPCI Memory Map Address Decoding with theL2 Cache System Clock GeneratorPPC Bus Arbitration PCI Host Bridgesupported. The Raven supports PowerPC processor external bus frequencies up to 66 MHz and PCI frequencies up to 33 MHz. The Raven is connected to the processor data parity signals to provide processor data bus parity generation and checking PCI Arbitration Interrupt HandlingSources of Reset ISA DMA ChannelsTable 2-2. Classes of Reset and Effectiveness Power-On Reset Undervoltage ResetFront Panel Push Button Reset CompactPCI Reset RST#Endian Issues Software ResetsReset Source Identification Processor/Memory DomainRole of the Raven ASIC PCI DomainPCI and Ethernet Startup and Operation 2-14Computer Group Literature Center Web Site PPCBug PPCBug OverviewPPCBug Basics Breakpoint and tracing capabilities MPU, Hardware, and Firmware Initialization Memory RequirementsPPCBug Implementation 7. Calculate the external bus clock speed of the MPU Using PPCBug Debugger Commands Table 3-1. Debugger Commands Table 3-1. Debugger Commands Continued CommandDescription Table 3-1. Debugger Commands Continued CommandDescription Diagnostic Tests Table 3-1. Debugger Commands ContinuedTable 3-2. Diagnostic Test Groups Notes You may enter command names in either uppercase or lowercase MCPN750A, unless SCSI or Video PMCs are installedTest Sets marked with an asterisk * are not available on the PPCBugCNFG and ENV Commands OverviewCNFG - Configure Board Information Block Configuring the PPCBug Parameters ENV - Set EnvironmentAuto-Initialize of NVRAM Header Enable Y/N = Y? Network PReP-Boot Mode Enable Y/N = N?SCSI Bus Reset on Debugger Startup Y/N = N? Primary SCSI Bus Negotiations Type A/S/N = A?NVRAM Bootlist GEV.fw-boot-path Boot Enable Y/N = N? NVRAM Bootlist GEV.fw-boot-path Boot at power-up only Y/N = N?NVRAM Bootlist GEV.fw-boot-path Boot Abort Delay = 5? Auto Boot Enable Y/N = N?Default = $00 ROM Boot Enable Y/N = N? ROM Boot at power-up only Y/N = Y?ROM Boot Abort Delay = 5? ROM Boot Direct Starting Address = FFF00000?If you use the NIOT debugger command, these parameters need The default Starting Address is $00000000 Note This parameter above also applies to enabling ECC for DRAM seconds LO, TA, VE Firmware Command Buffer ‘NULL’ terminates entry?Remote Start Via the PCI Bus OverviewIntroduction A command data and result field. This field provides the data, if any, needed by the command and provides the response from PPCBug upon command completion. The meaning of the bits in this field are specific to each command opcode Command/response Register Description register description continuesBits 9 to 15 7 bit command option field. Each command specifies the particular meaning of each of the command option bits. Option bits which are unused are considered reserved and should be written to 0 to ensure compatibility with future implementations of this interface Opcode 0x01 Write/Read Virtual Register Opcode 0x02 Initialize MemoryOpcode 0x03 Write/Read Memory Opcode 0x04 Checksum MemoryOpcode 0x05 Memory Size Query Opcode 0x06 Debugger QueryOpcode 0x07 Execute Code Command/Response Channel Error Codes Table 5-1. Command/Respond Error CodesDemonstration of the Host Interface MCPN750A target ConsoleMCP750 host Console MCPN750A target ConsoleStart the program from the host console MCP750 host ConsoleMCPN750A target Console PPC1-Bugm 8000EFC4cr8000EFC4 08030086? 00008007=cr 8000EFC4 00000007? .cr PPC1-Bug PPC1-Bug Host wrote 0004 to upper half of VR0Reference Function sromcrc.c Introduction crcflipped = 1 dbit = crc & 1 crc = 1 crcflipped += dbitcrc = crcflipped 0xffffffff return crc & 0xffff Remote Start Via the PCI Bus 5-14Computer Group Literature Center Web Site Features Table 6-1. MCPN750A FeaturesFunctional Description IntroductionTable 6-1. MCPN750A Features Continued General DescriptionBlock Diagram Figure 6-1. MCPN750A Block Diagram Debug Connector33MHz 32/64-bit PCI Local Bus 33MHz 32/64-bit CompactPCI BusCompactPCI Bus Interface Ethernet Interface PCI Mezzanine Interface PMC ConnectorsSignalling Voltage Mezzanine TypeConfiguration and Status Registers ISA Bus DevicesSerial EEPROM Asynchronous Serial PortsPCI Peripheral Bus Controller PBC ISA InterfaceEIDE Interface USB InterfaceISA Interrupt Controller ISA DMA ChannelsReal-Time Clock/NVRAM/Watchdog Timer Function Interval TimersReplacing Lithium Batteries Use ESD Wrist Strap Programmable Timers Raven General Purpose TimersHot Swap Control Circuitry Raven Watchdog Timers M48T559 Watchdog TimerSerial Port Signal Multiplexing Interval TimersFigure 6-2. Serial Port Signal Multiplexing I/O Signal Multiplexing IOMXIOMX Function Table 6-2. Multiplexing Sequence of the MX Function ABORT ABT/RESET RST Switch S1 Figure 6-3. MX Signal Timings Signal DescriptionsSerial Ports Defined Front Panel Indicators DS1 - DS3 MPC750 ProcessorRaven PCI-Host Bridge Flash MemoryBank A Flash Programming Enable JTAG/COPECC Memory Controller DRAM MemoryCompact FLASH Memory Card TMCPN710 Transition Module TM-PIMC-0001One standard 50-pin CompactFlash socket for IDE Flash Functional Description6-24 Computer Group Literature Center Web SiteConnector Pin Assignments MCPN750A and Transition Module ConnectorsMCPN750A Connector Pin Assignments MCPN750A CompactPCI Bus Connectors J1/J2Table 7-1. MCPN750A J1 CompactPCI Connector Table 7-1. MCPN750A J1 CompactPCI Connector Continued Table 7-2. MCPN750A J2 CompactPCI ConnectorBRSVP2B18 BRSVP2C18MCPN750A CompactPCI User I/O Connector J3 Table 7-2. MCPN750A J2 CompactPCI Connector ContinuedTable 7-3. MCPN750A J3 User I/O Connector Signal DescriptionsMCPN750A Connector J4 MCPN750A CompactPCI User I/O Connector J5 Table 7-4. MCPN750A J5 User I/O ConnectorSignal Descriptions PMCIO PMC2IO 164 - PMC 2 I/O signals 1 throughMCPN750A PCI Mezzanine Card Connectors J11/21, J12/22, J13/23, J14/24 Table 7-5. MCPN750A PCI Mezzanine Card ConnectorTable 7-5. MCPN750A PCI Mezzanine Card Connector Continued Table 7-6. MCPN750A PCI Mezzanine Card ConnectorTable 7-6. MCPN750A PCI Mezzanine Card Connector Continued MCPN750A 10BaseT/100BaseTx Connector J18 MCPN750A Debug Connector J19Table 7-7. MCPN750A 10BaseT/100BaseTx Connector J18 Table 7-8. MCPN750A Debug Connector J19 Table 7-8. MCPN750A Debug Connector J19 Continued Table 7-8. MCPN750A Debug Connector J19 Continued Table 7-8. MCPN750A Debug Connector J19 Continued MCPN750A Processor RISCWatch Debug Connector J6 Table 7-9. MCPN750A RISCWatch Debug Connector J6TMCPN710 Transition Module CompactPCI Connectors J3/J4/J5 TMCPN710 Transition ModuleTMCPN710 Transition Module COM1 Connector J6 Table 7-10. TMCPN710 COM1 Connector J6TMCPN710 Transition Module COM2 Connector J8 Table 7-11. TMCPN710 COM2 Connector J8TMCPN710 Transition Module COM3 Header J11 Table 7-12. TMCPN710 COM3/COM4 HeadersTMCPN710 Transition Module COM4 Header J14 Table 7-12. TMCPN710 COM3/COM4 HeadersSame as above TMCPN710 Transition Module 10BaseT/100BaseTx Connector J13 Table 7-13. TMCPN710 10BaseT/100BaseTx Connector J13TMCPN710 Transition Module USB Connectors J10, J12 TMCPN710TransitionModuleIDECompactFLASHConnectors J15, J16Table 7-14. TMCPN710 USB 0 Connector J10 Table 7-15. TMCPN710 USB 1 Connector J12Table 7-16. TMCPN710 Compact FLASH IDE Connectors TMCPN710 Transition Module PMC I/O Connectors J1/J2 Table 7-17. TMCPN710 PMC 1 and 2 I/O ConnectorTable 7-17. TMCPN710 PMC 1 and 2 I/O Connector SignalSignal TM-PIMC-0001 CompactPCI User I/O Connector J3, J4, & J5 TM-PIMC-0001 Transition ModuleTM-PIMC-0001 Transition Module COM1 Connector J9 Table 7-18. TM-PIMC-0001 COM1 Connector J9TM-PIMC-0001 Transition Module COM2 Connector J8 Table 7-19. TM-PIMC-0001 COM2 Connector J8TM-PIMC-0001 Transition Module COM3 and COM4 Connectors J12 & J13 Table 7-20. TM-PIMC-0001 COM3 and COM4 HeadersTM-PIMC-0001 Transition Module 10BaseT/100BaseTx Connector J7 TM-PIMC-0001 Transition Module IDE Compact FLASH Connector J1Table 7-21. TM-PIMC-0001 10BaseT/100BaseTx Connector J7 Table 7-22. TM-PIMC-0001 CompactFLASH IDE Connector J1 Connector Pin Assignments Table 7-23. TM-PIMC-0001 PMC I/O Module 1 PIM1 - Host I/OConnector Pin Assignments Continued Table 7-24. TM-PIMC-0001 PMC I/O Module 2 PIM2 - Host I/OConnector Pin Assignments Table 7-23. TM-PIMC-0001 PMC I/O Module 1 PIM1 - Host I/OConnector Pin Assignments Continued Note PMC I/O modules only use power, ground and the OUT-going serial port pins on the Host I/O connectors. With certain modifications, it is possible for a host I/O module to use all pins except the OUT-going serial portTable 7-24. TM-PIMC-0001 PMC I/O Module 2 PIM2 - Host I/O PMC I/O Connector Pin Assignments Table 7-25. PMC I/O Modules 1 and 2 PIM1 and PIM2J14/J24 PMC I/O Connector Pin Assignments Continued Table 7-25. PMC I/O Modules 1 and 2 PIM1 and PIM2PMC IO55 Connector Pin Assignments 7-38Computer Group Literature Center Web Site ASpecifications SpecificationsTable A-1. MCPN750A Specifications Cooling Requirements EMC Compliance Specifications Computer Group Literature Center Web SiteBRelated Documentation Motorola Computer Group DocumentsTable B-1. Motorola Computer Group Documents Manufacturers’ Documents Table B-2. Manufacturers’ DocumentsTable B-2. Manufacturers’ Documents Continued http//developer.intel.com/design/network/manuals/278074.htmhttp//developer.intel.com/design/bridge/datashts http//eu.st.com/stonline/index.shtmlRelated Specifications Table B-3. Related SpecificationsTable B-3. Related Specifications Continued Related SpecificationsTable B-3. Related Specifications Continued Index NumericsI N D E I N D E I N D E IN-4I N D E I N D E IN-6I N D E I N D E IN-8I N D E X IN-9I N D E X IN-10