
Block Diagram
CompactPCI Bus Interface
The CompactPCI bus interface is provided using the Intel 21554 non- transparent
Unlike a transparent
The 21554 also provides for independent primary and secondary PCI clocks which means that the MCPN750A SBC has it’s own local processor/PCI bus clock source independent of the system backplane clocks.
The 21554 has an I2O message unit which enables the local processor to function as an intelligent I/O processor in an I2O capable system. The device also has an interrupt output for each of the primary and secondary PCI buses. These interrupts may be asserted by the I2O messaging unit or by software writes to an interrupt request register.
The 21554 supports +3.3V or +5V signalling at the PCI buses with a separate VIO pin for the primary and secondary bus I/O’s. The secondary bus signalling voltage is tied to +5V for compatibility with +5V PMCs. The primary bus signalling voltage is tied to the CPCI bus VIO, so the MCPN750A is a universal board that may operate in a +3.3V or +5V chassis.
6 |
http://www.motorola.com/computer/literature |