Motorola IH5, MCPN750A manual Prst

Auto-Initialize of NVRAM Header En- able 4-4

Bug or System explained 4-3DRAM Parity Enable 4-10

DRAM Speed in NANO Seconds 4-9Field Service Menu Enable explained

4-3

L2 Cache Parity Enable 4-10Memory Size Enable 4-9Memory Size Ending Address 4-9Memory Size Starting Address 4-9Network Auto Boot Abort Delay 4-8Network Auto Boot at power-up 4-7Network Auto Boot Configuration Pa-

rameters Offset 4-8Network Auto Boot Controller LUN 4-8Network Auto Boot Device LUN 4-8Network Auto Boot Enable 4-7Network PRep-Boot Mode Enable 4-4NVRAM Bootlist Boot at Power-up only

4-5

NVRAM Bootlist Boot Enable 4-5

PCI Interrupts Route Control Registers 4-10

Primary SCSI Bus Negotiations Type 4-4

Primary SCSI Data Bus Width 4-4Probe System for Supported I/O Con-

trollers 4-3ROM Boot Abort Delay 4-7

ROM Boot at power-up only 4-7ROM Boot Direct Ending Address 4-7ROM Boot Direct Starting Address 4-7ROM Boot Enable 4-7

ROM First Access Length 4-9

SCSI Bus Reset on Debugger Startup 4-4secondary SCSI controller 4-4

Serial Startup Code LF Enable 4-11Serial Startup Code Master Enable 4-11

PPCBug parameters 4-1changing 4-1configurable by ENV 4-3

prompt, debugger 3-11

PRST

as reset source 2-10push button reset 2-11

R

RAM

for timer functions 6-11Raven ASIC

as MPIC Interrupt Controller 2-8

as MPU/PCI bus bridge controller 2-3,6-20

general purpose timers 6-14role in endian issues 2-13Watchdog timers 6-15

Raven MPU/PCI bus bridge controller ASIC 2-12

Raven/Falcon role 2-3

real-timeclock 6-11registers

configuration and status 6-8related specifications B-4remote command

channel 5-1

remote control/status connector 6-16remote interface

via cPCI bus 5-1Remote Start

example 5-9reset

CompactPCI 2-11power-on 2-11software 2-12undervoltage 2-11Watchdog Timer 2-11

RESET switch

as hard reset 2-9resets

devices affected 2-10resetting the system 2-9restart mode 3-12

I

N D E X

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