Motorola IH5, MCPN750A manual ISA DMA Channels, Sources of Reset

Memory Maps

❏The Processor 0 (processor self-interrupts)

❏Transfer Error Interrupt (from the Raven ASIC)

❏The Falcon chip set (memory error interrupts)

❏The PCI bus (interrupts from PCI devices)

❏The CPCI bus (interrupts from CPCI devices)

❏Power monitor interrupts

❏Watchdog timer interrupt

❏The ISA bus (interrupts from ISA devices)

The ISA interrupts are handled as a single 8259 interrupt from the VT82C586B PBC device.

For details on interrupt handling, refer to the MCPN750A CompactPCI Single Board Computer Programmer’s Reference Guide (MCPN750A/PG).

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ISA DMA Channels

The PBC supports seven 8237 compatible DMA channels. ISA compatible type A, B and F timing is supported. These DMA channels are not used since there are no ISA DMA devices.

Sources of Reset

The MCPN750A SBC provides reset control from various sources and identifies the source of the reset in a software readable register. Hard or soft resets may be generated. A hard reset is defined as a reset of all onboard circuitry including the PowerPC hard reset and reset of all onboard peripheral devices. A soft reset is defined as a reset of the PowerPC. The MCPN750A SBC has seven potential sources of reset:

1.Power-on/Undervoltage Reset.

2.Front Panel RESET switch (will generate a hard reset when depressed).

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