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Motorola IH5 NVRAM Bootlist GEV.fw-boot-path Boot Enable Y/N = N?, Auto Boot Enable Y/N = N?

Models: IH5 MCPN750A

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NVRAM Bootlist (GEV.fw-boot-path) Boot Enable [Y/N] = N?

ENV - Set Environment

NVRAM Bootlist (GEV.fw-boot-path) Boot Enable [Y/N] = N?

YGive boot priority to devices defined in the fw-boot- path global environment variable (GEV).

NDo not give boot priority to devices listed in the fw- boot-pathGEV. (Default)

Note When enabled, the GEV (Global Environment Variable) boot takes priority over all other boots, including Autoboot and Network Boot.

NVRAM Bootlist (GEV.fw-boot-path) Boot at power-up only [Y/N] = N?

YGive boot priority to devices defined in the fw-boot- path GEV at power-up reset only.

NGive power-up boot priority to devices listed in the fw-boot-pathGEV at any reset. (Default)

NVRAM Bootlist (GEV.fw-boot-path) Boot Abort Delay = 5?

The time in seconds that a boot from the NVRAM boot list will delay before starting the boot. The purpose for the delay is to allow you the option of stopping the boot by use of the BREAK key. The time value is from 0-255 seconds. (Default = 5 seconds)

Auto Boot Enable [Y/N] = N?

YThe Autoboot function is enabled.

NThe Autoboot function is disabled. (Default)

Auto Boot at power-up only [Y/N] = N?

YAutoboot is attempted at power-up reset only.

NAutoboot is attempted at any reset. (Default)

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Motorola IH5 NVRAM Bootlist GEV.fw-boot-path Boot Enable Y/N = N?, NVRAM Bootlist GEV.fw-boot-path Boot Abort Delay = 5?

Contents

September 2001 Edition Installation and UseMCPN750A CompactPCI Single Board Computer MCPN750A/IH5Printed in the United States of America Copyright 2001 Motorola, Inc All Rights ReservedDo Not Operate in an Explosive Atmosphere Safety SummaryUse Caution When Exposing or Handling a CRT Ground the Instrumentinstructions Lithium Battery CautionFlammability EMI CautionCE Notice European Community Limited and Restricted Rights Legend About This Manual ContentsCHAPTER 1 Hardware Preparation and Installation CHAPTER 3 PPCBug CHAPTER 2 Startup and OperationCHAPTER 6 Functional Description CHAPTER 4 CNFG and ENV CommandsCHAPTER 5 Remote Start Via the PCI Bus CHAPTER 7 Connector Pin Assignments Related Documentation SpecificationsAPPENDIX A APPENDIX BPage List of Figures Page List of Tables Table 7-25. PMC I/O Modules 1 and 2 PIM1 and PIM2 Currently, the boards are provided in the following configurations About This ManualChanges Overview of ContentsSummary of Changes DateComments and Suggestions CTRL Conventions Used in This Manualbold Enter, Return or CRProduct Description Hardware Preparation and InstallationBlock Diagram Introduction33MHz 32/64-bit CompactPCI Bus Figure 1-1. MCPN750A Baseboard Block DiagramDebug Connector 33MHz 32/64-bit PCI Local BusTable 1-1. Startup Overview Overview of Start-up ProcedureGetting Started Table 1-1. Startup Overview Continued Equipment RequiredUnpacking Instructions ESD PrecautionsMCPN750A Baseboard Preparation Hardware ConfigurationPreparation Preparation Flash Bank Selection J7Stand-Alone Operating Mode J8 2703 LEDsFuses,Connectors,Headers,MCPN750AFigure 1-2.Switches System Considerations TMCPN710 Transition Module Preparation Computer Group Literature Center Web Site Figure 1-3. TMCPN710 Connector and Header LocationsHardware Preparation and Installation 1-12Serial Ports 1 and TMCPN710 Figure 1-4. MCPN750A/TMCPN710 Serial Ports 1 andMCPN750A RJ45TMCPN710 COM3 and COM4 Asynchronous Serial PortsFigure 1-5. TMCPN710 Serial Ports 3 and MCPN750ATM-PIMC-0001 Transition Module Preparation 2694 Connector and Header LocationsFigure 1-6. TM-PIMC-0001 COM1 and COM2 Asynchronous Serial Ports RJ45 Figure 1-7. MCPN750A/TM-PIMC-0001 Serial Ports 1 andMCPN750 TM-PIMC-0001COM3 and COM4 Asynchronous Serial Ports Figure 1-8. TM-PIMC-0001 Serial Ports 3 andThe signals for COM3 and COM4 serial ports are routed to 10-pin headers on the TM-PIMC-0001 Transition Module J12 and J13. These headers function as I/O connectors for the MCPN750A and are permanently configured as DTE. Figure 1-8 depicts this configuration Installing PMC Modules on the MCPN750A SBC Hardware InstallationFigure 1-9. PMC Module Placement on MCPN750A 5. Remove the PMC filler from the front panel of the MCPN750A Installing the MCPN750A Baseboard Hardware Installation Installing PIMs on the TM-PIMC-0001 Transition Module Installing a TMCPN710 or TM-PIMC-0001 Transition ModuleFigure 1-10. Installing a PIM on the TM-PIMC-0001 Transition Module Installing the Transition Module in the Chassis Dangerous voltages, capable of causing death, are present in Computer Group Literature Center Web Site Figure 1-11. TMCPN710 or TM-PIMC-0001/MCPN750A Mating ConfigurationHardware Preparation and Installation 1-30Current Available to PMCs & Transition Modules MCPN750A Module Power RequirementsVoltage Computer Group Literature Center Web Site Hardware Preparation and Installation1-32 Introduction Applying PowerStartup and Operation STARTUP SYSTEM INITIALIZATION CONSOLE DETECTION RUN SELFTESTS Figure 2-1. PPCBug System StartupIF ENABLED AUTOBOOT IF ENABLED OPERATING SYSTEM Processor Memory Map Default Processor Memory MapTable 2-1. Processor Default View of the Memory Map Memory MapsPCI Local Bus Memory Map Table 2-1. Processor Default View of the Memory Map ContinuedAddress Decoding with the CompactPCI Memory MapPCI Host Bridge L2 CacheSystem Clock Generator PPC Bus Arbitrationsupported. The Raven supports PowerPC processor external bus frequencies up to 66 MHz and PCI frequencies up to 33 MHz. The Raven is connected to the processor data parity signals to provide processor data bus parity generation and checking Interrupt Handling PCI ArbitrationISA DMA Channels Sources of ResetTable 2-2. Classes of Reset and Effectiveness CompactPCI Reset RST# Power-On ResetUndervoltage Reset Front Panel Push Button ResetProcessor/Memory Domain Endian IssuesSoftware Resets Reset Source IdentificationPCI and Ethernet Role of the Raven ASICPCI Domain Computer Group Literature Center Web Site Startup and Operation2-14 PPCBug Basics PPCBugPPCBug Overview Breakpoint and tracing capabilities PPCBug Implementation MPU, Hardware, and Firmware InitializationMemory Requirements 7. Calculate the external bus clock speed of the MPU Using PPCBug Debugger Commands Table 3-1. Debugger Commands Description Table 3-1. Debugger Commands ContinuedCommand Description Table 3-1. Debugger Commands ContinuedCommand Table 3-1. Debugger Commands Continued Diagnostic TestsTable 3-2. Diagnostic Test Groups PPCBug Notes You may enter command names in either uppercase or lowercaseMCPN750A, unless SCSI or Video PMCs are installed Test Sets marked with an asterisk * are not available on theOverview CNFG and ENV CommandsCNFG - Configure Board Information Block ENV - Set Environment Configuring the PPCBug ParametersPrimary SCSI Bus Negotiations Type A/S/N = A? Auto-Initialize of NVRAM Header Enable Y/N = Y?Network PReP-Boot Mode Enable Y/N = N? SCSI Bus Reset on Debugger Startup Y/N = N?Auto Boot Enable Y/N = N? NVRAM Bootlist GEV.fw-boot-path Boot Enable Y/N = N?NVRAM Bootlist GEV.fw-boot-path Boot at power-up only Y/N = N? NVRAM Bootlist GEV.fw-boot-path Boot Abort Delay = 5?Default = $00 ROM Boot Direct Starting Address = FFF00000? ROM Boot Enable Y/N = N?ROM Boot at power-up only Y/N = Y? ROM Boot Abort Delay = 5?If you use the NIOT debugger command, these parameters need The default Starting Address is $00000000 Note This parameter above also applies to enabling ECC for DRAM seconds Firmware Command Buffer ‘NULL’ terminates entry? LO, TA, VEIntroduction Remote Start Via the PCI BusOverview A command data and result field. This field provides the data, if any, needed by the command and provides the response from PPCBug upon command completion. The meaning of the bits in this field are specific to each command opcode register description continues Command/response Register DescriptionBits 9 to 15 7 bit command option field. Each command specifies the particular meaning of each of the command option bits. Option bits which are unused are considered reserved and should be written to 0 to ensure compatibility with future implementations of this interface Opcode 0x02 Initialize Memory Opcode 0x01 Write/Read Virtual RegisterOpcode 0x04 Checksum Memory Opcode 0x03 Write/Read MemoryOpcode 0x07 Execute Code Opcode 0x05 Memory Size QueryOpcode 0x06 Debugger Query Table 5-1. Command/Respond Error Codes Command/Response Channel Error CodesMCPN750A target Console Demonstration of the Host InterfaceMCP750 host Console MCP750 host ConsoleMCPN750A target Console Start the program from the host consolePPC1-Bug Host wrote 0004 to upper half of VR0 MCPN750A target ConsolePPC1-Bugm 8000EFC4cr 8000EFC4 08030086? 00008007=cr 8000EFC4 00000007? .cr PPC1-BugReference Function sromcrc.c crc = crcflipped 0xffffffff return crc & 0xffff Introductioncrcflipped = 1 dbit = crc & 1 crc = 1 crcflipped += dbit Computer Group Literature Center Web Site Remote Start Via the PCI Bus5-14 Introduction FeaturesTable 6-1. MCPN750A Features Functional DescriptionGeneral Description Table 6-1. MCPN750A Features ContinuedBlock Diagram 33MHz 32/64-bit CompactPCI Bus Figure 6-1. MCPN750A Block DiagramDebug Connector 33MHz 32/64-bit PCI Local BusCompactPCI Bus Interface Ethernet Interface Mezzanine Type PCI Mezzanine InterfacePMC Connectors Signalling VoltageAsynchronous Serial Ports Configuration and Status RegistersISA Bus Devices Serial EEPROMISA Interface PCI Peripheral Bus Controller PBCISA DMA Channels EIDE InterfaceUSB Interface ISA Interrupt ControllerInterval Timers Real-Time Clock/NVRAM/Watchdog Timer FunctionReplacing Lithium Batteries Use ESD Wrist Strap Hot Swap Control Circuitry Programmable TimersRaven General Purpose Timers M48T559 Watchdog Timer Raven Watchdog TimersInterval Timers Serial Port Signal MultiplexingIOMX Function Figure 6-2. Serial Port Signal MultiplexingI/O Signal Multiplexing IOMX Table 6-2. Multiplexing Sequence of the MX Function Serial Ports Defined ABORT ABT/RESET RST Switch S1Figure 6-3. MX Signal Timings Signal Descriptions Flash Memory Front Panel Indicators DS1 - DS3MPC750 Processor Raven PCI-Host BridgeJTAG/COP Bank A Flash Programming EnableCompact FLASH Memory Card ECC Memory ControllerDRAM Memory TM-PIMC-0001 TMCPN710 Transition ModuleComputer Group Literature Center Web Site One standard 50-pin CompactFlash socket for IDE FlashFunctional Description 6-24MCPN750A and Transition Module Connectors Connector Pin AssignmentsTable 7-1. MCPN750A J1 CompactPCI Connector MCPN750A Connector Pin AssignmentsMCPN750A CompactPCI Bus Connectors J1/J2 BRSVP2C18 Table 7-1. MCPN750A J1 CompactPCI Connector ContinuedTable 7-2. MCPN750A J2 CompactPCI Connector BRSVP2B18Table 7-2. MCPN750A J2 CompactPCI Connector Continued MCPN750A CompactPCI User I/O Connector J3Signal Descriptions Table 7-3. MCPN750A J3 User I/O ConnectorMCPN750A Connector J4 Table 7-4. MCPN750A J5 User I/O Connector MCPN750A CompactPCI User I/O Connector J5PMCIO PMC2IO 164 - PMC 2 I/O signals 1 through Signal DescriptionsTable 7-5. MCPN750A PCI Mezzanine Card Connector MCPN750A PCI Mezzanine Card Connectors J11/21, J12/22, J13/23, J14/24Table 7-6. MCPN750A PCI Mezzanine Card Connector Table 7-5. MCPN750A PCI Mezzanine Card Connector ContinuedTable 7-6. MCPN750A PCI Mezzanine Card Connector Continued Table 7-7. MCPN750A 10BaseT/100BaseTx Connector J18 MCPN750A 10BaseT/100BaseTx Connector J18MCPN750A Debug Connector J19 Table 7-8. MCPN750A Debug Connector J19 Table 7-8. MCPN750A Debug Connector J19 Continued Table 7-8. MCPN750A Debug Connector J19 Continued Table 7-8. MCPN750A Debug Connector J19 Continued Table 7-9. MCPN750A RISCWatch Debug Connector J6 MCPN750A Processor RISCWatch Debug Connector J6TMCPN710 Transition Module TMCPN710 Transition Module CompactPCI Connectors J3/J4/J5Table 7-10. TMCPN710 COM1 Connector J6 TMCPN710 Transition Module COM1 Connector J6Table 7-12. TMCPN710 COM3/COM4 Headers TMCPN710 Transition Module COM2 Connector J8Table 7-11. TMCPN710 COM2 Connector J8 TMCPN710 Transition Module COM3 Header J11Same as above TMCPN710 Transition Module COM4 Header J14Table 7-12. TMCPN710 COM3/COM4 Headers Table 7-13. TMCPN710 10BaseT/100BaseTx Connector J13 TMCPN710 Transition Module 10BaseT/100BaseTx Connector J13Table 7-15. TMCPN710 USB 1 Connector J12 TMCPN710 Transition Module USB Connectors J10, J12TMCPN710TransitionModuleIDECompactFLASHConnectors J15, J16 Table 7-14. TMCPN710 USB 0 Connector J10Table 7-16. TMCPN710 Compact FLASH IDE Connectors Table 7-17. TMCPN710 PMC 1 and 2 I/O Connector TMCPN710 Transition Module PMC I/O Connectors J1/J2Signal Table 7-17. TMCPN710 PMC 1 and 2 I/O ConnectorSignal TM-PIMC-0001 Transition Module TM-PIMC-0001 CompactPCI User I/O Connector J3, J4, & J5Table 7-18. TM-PIMC-0001 COM1 Connector J9 TM-PIMC-0001 Transition Module COM1 Connector J9Table 7-19. TM-PIMC-0001 COM2 Connector J8 TM-PIMC-0001 Transition Module COM2 Connector J8Table 7-20. TM-PIMC-0001 COM3 and COM4 Headers TM-PIMC-0001 Transition Module COM3 and COM4 Connectors J12 & J13Table 7-21. TM-PIMC-0001 10BaseT/100BaseTx Connector J7 TM-PIMC-0001 Transition Module 10BaseT/100BaseTx Connector J7TM-PIMC-0001 Transition Module IDE Compact FLASH Connector J1 Table 7-22. TM-PIMC-0001 CompactFLASH IDE Connector J1 Table 7-23. TM-PIMC-0001 PMC I/O Module 1 PIM1 - Host I/O Connector Pin AssignmentsTable 7-23. TM-PIMC-0001 PMC I/O Module 1 PIM1 - Host I/O Connector Pin Assignments ContinuedTable 7-24. TM-PIMC-0001 PMC I/O Module 2 PIM2 - Host I/O Connector Pin AssignmentsTable 7-24. TM-PIMC-0001 PMC I/O Module 2 PIM2 - Host I/O Connector Pin Assignments ContinuedNote PMC I/O modules only use power, ground and the OUT-going serial port pins on the Host I/O connectors. With certain modifications, it is possible for a host I/O module to use all pins except the OUT-going serial port J14/J24 PMC I/O Connector Pin AssignmentsTable 7-25. PMC I/O Modules 1 and 2 PIM1 and PIM2 PMC IO55 PMC I/O Connector Pin Assignments ContinuedTable 7-25. PMC I/O Modules 1 and 2 PIM1 and PIM2 Computer Group Literature Center Web Site Connector Pin Assignments7-38 Table A-1. MCPN750A Specifications ASpecificationsSpecifications Cooling Requirements EMC Compliance Computer Group Literature Center Web Site SpecificationsTable B-1. Motorola Computer Group Documents BRelated DocumentationMotorola Computer Group Documents Table B-2. Manufacturers’ Documents Manufacturers’ Documentshttp//eu.st.com/stonline/index.shtml Table B-2. Manufacturers’ Documents Continuedhttp//developer.intel.com/design/network/manuals/278074.htm http//developer.intel.com/design/bridge/datashtsTable B-3. Related Specifications Related SpecificationsRelated Specifications Table B-3. Related Specifications ContinuedTable B-3. Related Specifications Continued Numerics IndexI N D E I N D E IN-4 I N D EI N D E IN-6 I N D EI N D E IN-8 I N D EIN-9 I N D E XIN-10 I N D E X