Memory Maps
For detailed PCI memory maps, including suggested
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CompactPCI Memory Map
The MCPN750A uses the 21554
Address Decoding with the 21554
The 21554 implements multiple base address registers on both the primary and secondary interfaces that denote separate address ranges for both downstream and upstream transactions. It also has base registers for access to its Control and Status Register (CSR) space. Consequently, on the primary interface (CompactPCI bus) the 21554 responds only to those transactions which are in the address range defined by one of the base address ranges. All other addresses are ignored. The same is true for transactions on the secondary interface (local PCI bus).
The address ranges defined by the primary base address registers reside in the primary or system address map. The address ranges defined by the secondary base address registers reside in the secondary or local address map. Each of these address maps is independent of each other. The 21554 provide address translation between these two address maps when forwarding transactions upstream or downstream.
Recommendations for CompactPCI mapping, including suggested PREP- compatible memory maps, can be found in the MCPN750A CompactPCI Single Board Computer Programmer’s Reference Guide (MCPN750A/PG).
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