Motorola IH5, MCPN750A manual MPU, Hardware, and Firmware Initialization, Memory Requirements

Models: IH5 MCPN750A

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Memory Requirements

MPU, Hardware, and Firmware Initialization

Memory Requirements

PPCBug requires a maximum of 768KB of read/write memory (i.e., DRAM). The debugger allocates this space from the top of memory. For example, a system containing 64MB ($04000000) of read/write memory will place the PPCBug memory page at locations $03F80000 to $03FFFFFF.

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PPCBug Implementation

PPCBug is written largely in the C programming language, providing benefits of portability and maintainability. Where necessary, assembly language has been used in the form of separately compiled program modules containing only assembler code. No mixed-language modules are used.

Physically, PPCBug is contained in two socketed 32-pin PLCC Flash devices that together provide 1MB of storage. The executable code is checksummed at every power-on or reset firmware entry, and the result (which includes a precalculated checksum contained in the Flash devices), is verified against the expected checksum.

MPU, Hardware, and Firmware Initialization

The debugger performs the MPU, hardware, and firmware initialization process. This process occurs each time the MCPN750A is reset or powered up. The steps below are a high-level outline; not all of the detailed steps are listed.

1.Sets MPU.MSR to known value.

2.Invalidates the MPU’s data/instruction caches.

3.Clears all segment registers of the MPU.

4.Clears all block address translation registers of the MPU.

5.Initializes the MPU-bus-to-PCI-bus bridge device.

6.Initializes the PCI-bus-to-ISA-bus bridge device.

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Page 69
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Motorola IH5, MCPN750A manual MPU, Hardware, and Firmware Initialization, Memory Requirements, PPCBug Implementation