5 |
Remote Start Via the PCI Bus
❏The state of CPU registers R0 through R2, and R4 through R31 are indeterminate when control is passed to the address.
❏Note: this command does not return. The OWN flag bit remains clear.
Command/Response Channel Error Codes
These are the 16 bit values that the target board returns in the Data/Result field of the Command/Response register when the target board detects an error in the processing of a host command. These error codes are valid only if the ERR bit was set in the Command/Response register.
Table 5-1. Command/Respond Error Codes
Error | Associated | Definition of the Error Code | |
Code | Opcode:Command | ||
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0x0001 | 0x03:Write/Read | illegal access size requested | |
| memory |
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0x0002 | n/a | unsupported command opcode requested | |
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