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Motorola MCPN750A, IH5 Connector Pin Assignments, 7-38, Computer Group Literature Center Web Site

Models: IH5 MCPN750A

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Motorola MCPN750A, IH5 manual Connector Pin Assignments, 7-38, Computer Group Literature Center Web Site

Contents

MCPN750A/IH5 Installation and UseMCPN750A CompactPCI Single Board Computer September 2001 EditionCopyright 2001 Motorola, Inc All Rights Reserved Printed in the United States of AmericaGround the Instrument Safety SummaryUse Caution When Exposing or Handling a CRT Do Not Operate in an Explosive AtmosphereEMI Caution Lithium Battery CautionFlammability instructionsCE Notice European Community Limited and Restricted Rights Legend CHAPTER 1 Hardware Preparation and Installation ContentsAbout This Manual CHAPTER 2 Startup and Operation CHAPTER 3 PPCBugCHAPTER 5 Remote Start Via the PCI Bus CHAPTER 4 CNFG and ENV CommandsCHAPTER 6 Functional Description CHAPTER 7 Connector Pin Assignments APPENDIX B SpecificationsAPPENDIX A Related DocumentationPage List of Figures Page List of Tables Table 7-25. PMC I/O Modules 1 and 2 PIM1 and PIM2 About This Manual Currently, the boards are provided in the following configurationsDate Overview of ContentsSummary of Changes ChangesComments and Suggestions Enter, Return or CR Conventions Used in This Manualbold CTRLIntroduction Hardware Preparation and InstallationBlock Diagram Product Description33MHz 32/64-bit PCI Local Bus Figure 1-1. MCPN750A Baseboard Block DiagramDebug Connector 33MHz 32/64-bit CompactPCI BusGetting Started Overview of Start-up ProcedureTable 1-1. Startup Overview Equipment Required Table 1-1. Startup Overview ContinuedESD Precautions Unpacking InstructionsPreparation Hardware ConfigurationMCPN750A Baseboard Preparation Flash Bank Selection J7 PreparationStand-Alone Operating Mode J8 Fuses,Connectors,Headers,MCPN750AFigure 1-2.Switches LEDs2703 System Considerations TMCPN710 Transition Module Preparation 1-12 Figure 1-3. TMCPN710 Connector and Header LocationsHardware Preparation and Installation Computer Group Literature Center Web SiteSerial Ports 1 and RJ45 Figure 1-4. MCPN750A/TMCPN710 Serial Ports 1 andMCPN750A TMCPN710MCPN750A COM3 and COM4 Asynchronous Serial PortsFigure 1-5. TMCPN710 Serial Ports 3 and TMCPN710TM-PIMC-0001 Transition Module Preparation Figure 1-6. TM-PIMC-0001 Connector and Header Locations2694 COM1 and COM2 Asynchronous Serial Ports TM-PIMC-0001 Figure 1-7. MCPN750A/TM-PIMC-0001 Serial Ports 1 andMCPN750 RJ45The signals for COM3 and COM4 serial ports are routed to 10-pin headers on the TM-PIMC-0001 Transition Module J12 and J13. These headers function as I/O connectors for the MCPN750A and are permanently configured as DTE. Figure 1-8 depicts this configuration Figure 1-8. TM-PIMC-0001 Serial Ports 3 andCOM3 and COM4 Asynchronous Serial Ports Hardware Installation Installing PMC Modules on the MCPN750A SBCFigure 1-9. PMC Module Placement on MCPN750A 5. Remove the PMC filler from the front panel of the MCPN750A Installing the MCPN750A Baseboard Hardware Installation Installing a TMCPN710 or TM-PIMC-0001 Transition Module Installing PIMs on the TM-PIMC-0001 Transition ModuleFigure 1-10. Installing a PIM on the TM-PIMC-0001 Transition Module Installing the Transition Module in the Chassis Dangerous voltages, capable of causing death, are present in 1-30 Figure 1-11. TMCPN710 or TM-PIMC-0001/MCPN750A Mating ConfigurationHardware Preparation and Installation Computer Group Literature Center Web SiteVoltage MCPN750A Module Power RequirementsCurrent Available to PMCs & Transition Modules 1-32 Hardware Preparation and InstallationComputer Group Literature Center Web Site Startup and Operation Applying PowerIntroduction IF ENABLED AUTOBOOT IF ENABLED OPERATING SYSTEM Figure 2-1. PPCBug System StartupSTARTUP SYSTEM INITIALIZATION CONSOLE DETECTION RUN SELFTESTS Memory Maps Default Processor Memory MapTable 2-1. Processor Default View of the Memory Map Processor Memory MapTable 2-1. Processor Default View of the Memory Map Continued PCI Local Bus Memory MapCompactPCI Memory Map Address Decoding with thePPC Bus Arbitration L2 CacheSystem Clock Generator PCI Host Bridgesupported. The Raven supports PowerPC processor external bus frequencies up to 66 MHz and PCI frequencies up to 33 MHz. The Raven is connected to the processor data parity signals to provide processor data bus parity generation and checking PCI Arbitration Interrupt HandlingSources of Reset ISA DMA ChannelsTable 2-2. Classes of Reset and Effectiveness Front Panel Push Button Reset Power-On ResetUndervoltage Reset CompactPCI Reset RST#Reset Source Identification Endian IssuesSoftware Resets Processor/Memory DomainPCI Domain Role of the Raven ASICPCI and Ethernet 2-14 Startup and OperationComputer Group Literature Center Web Site PPCBug Overview PPCBugPPCBug Basics Breakpoint and tracing capabilities Memory Requirements MPU, Hardware, and Firmware InitializationPPCBug Implementation 7. Calculate the external bus clock speed of the MPU Using PPCBug Debugger Commands Table 3-1. Debugger Commands Command Table 3-1. Debugger Commands ContinuedDescription Command Table 3-1. Debugger Commands ContinuedDescription Diagnostic Tests Table 3-1. Debugger Commands ContinuedTable 3-2. Diagnostic Test Groups Test Sets marked with an asterisk * are not available on the Notes You may enter command names in either uppercase or lowercaseMCPN750A, unless SCSI or Video PMCs are installed PPCBugCNFG and ENV Commands OverviewCNFG - Configure Board Information Block Configuring the PPCBug Parameters ENV - Set EnvironmentSCSI Bus Reset on Debugger Startup Y/N = N? Auto-Initialize of NVRAM Header Enable Y/N = Y?Network PReP-Boot Mode Enable Y/N = N? Primary SCSI Bus Negotiations Type A/S/N = A?NVRAM Bootlist GEV.fw-boot-path Boot Abort Delay = 5? NVRAM Bootlist GEV.fw-boot-path Boot Enable Y/N = N?NVRAM Bootlist GEV.fw-boot-path Boot at power-up only Y/N = N? Auto Boot Enable Y/N = N?Default = $00 ROM Boot Abort Delay = 5? ROM Boot Enable Y/N = N?ROM Boot at power-up only Y/N = Y? ROM Boot Direct Starting Address = FFF00000?If you use the NIOT debugger command, these parameters need The default Starting Address is $00000000 Note This parameter above also applies to enabling ECC for DRAM seconds LO, TA, VE Firmware Command Buffer ‘NULL’ terminates entry?Overview Remote Start Via the PCI BusIntroduction A command data and result field. This field provides the data, if any, needed by the command and provides the response from PPCBug upon command completion. The meaning of the bits in this field are specific to each command opcode Command/response Register Description register description continuesBits 9 to 15 7 bit command option field. Each command specifies the particular meaning of each of the command option bits. Option bits which are unused are considered reserved and should be written to 0 to ensure compatibility with future implementations of this interface Opcode 0x01 Write/Read Virtual Register Opcode 0x02 Initialize MemoryOpcode 0x03 Write/Read Memory Opcode 0x04 Checksum MemoryOpcode 0x06 Debugger Query Opcode 0x05 Memory Size QueryOpcode 0x07 Execute Code Command/Response Channel Error Codes Table 5-1. Command/Respond Error CodesDemonstration of the Host Interface MCPN750A target ConsoleStart the program from the host console MCP750 host ConsoleMCPN750A target Console MCP750 host Console8000EFC4 08030086? 00008007=cr 8000EFC4 00000007? .cr PPC1-Bug MCPN750A target ConsolePPC1-Bugm 8000EFC4cr PPC1-Bug Host wrote 0004 to upper half of VR0Reference Function sromcrc.c crcflipped = 1 dbit = crc & 1 crc = 1 crcflipped += dbit Introductioncrc = crcflipped 0xffffffff return crc & 0xffff 5-14 Remote Start Via the PCI BusComputer Group Literature Center Web Site Functional Description FeaturesTable 6-1. MCPN750A Features IntroductionTable 6-1. MCPN750A Features Continued General DescriptionBlock Diagram 33MHz 32/64-bit PCI Local Bus Figure 6-1. MCPN750A Block DiagramDebug Connector 33MHz 32/64-bit CompactPCI BusCompactPCI Bus Interface Ethernet Interface Signalling Voltage PCI Mezzanine InterfacePMC Connectors Mezzanine TypeSerial EEPROM Configuration and Status RegistersISA Bus Devices Asynchronous Serial PortsPCI Peripheral Bus Controller PBC ISA InterfaceISA Interrupt Controller EIDE InterfaceUSB Interface ISA DMA ChannelsReal-Time Clock/NVRAM/Watchdog Timer Function Interval TimersReplacing Lithium Batteries Use ESD Wrist Strap Raven General Purpose Timers Programmable TimersHot Swap Control Circuitry Raven Watchdog Timers M48T559 Watchdog TimerSerial Port Signal Multiplexing Interval TimersI/O Signal Multiplexing IOMX Figure 6-2. Serial Port Signal MultiplexingIOMX Function Table 6-2. Multiplexing Sequence of the MX Function Figure 6-3. MX Signal Timings Signal Descriptions ABORT ABT/RESET RST Switch S1Serial Ports Defined Raven PCI-Host Bridge Front Panel Indicators DS1 - DS3MPC750 Processor Flash MemoryBank A Flash Programming Enable JTAG/COPDRAM Memory ECC Memory ControllerCompact FLASH Memory Card TMCPN710 Transition Module TM-PIMC-00016-24 One standard 50-pin CompactFlash socket for IDE FlashFunctional Description Computer Group Literature Center Web SiteConnector Pin Assignments MCPN750A and Transition Module ConnectorsMCPN750A CompactPCI Bus Connectors J1/J2 MCPN750A Connector Pin AssignmentsTable 7-1. MCPN750A J1 CompactPCI Connector BRSVP2B18 Table 7-1. MCPN750A J1 CompactPCI Connector ContinuedTable 7-2. MCPN750A J2 CompactPCI Connector BRSVP2C18MCPN750A CompactPCI User I/O Connector J3 Table 7-2. MCPN750A J2 CompactPCI Connector ContinuedTable 7-3. MCPN750A J3 User I/O Connector Signal DescriptionsMCPN750A Connector J4 MCPN750A CompactPCI User I/O Connector J5 Table 7-4. MCPN750A J5 User I/O ConnectorSignal Descriptions PMCIO PMC2IO 164 - PMC 2 I/O signals 1 throughMCPN750A PCI Mezzanine Card Connectors J11/21, J12/22, J13/23, J14/24 Table 7-5. MCPN750A PCI Mezzanine Card ConnectorTable 7-5. MCPN750A PCI Mezzanine Card Connector Continued Table 7-6. MCPN750A PCI Mezzanine Card ConnectorTable 7-6. MCPN750A PCI Mezzanine Card Connector Continued MCPN750A Debug Connector J19 MCPN750A 10BaseT/100BaseTx Connector J18Table 7-7. MCPN750A 10BaseT/100BaseTx Connector J18 Table 7-8. MCPN750A Debug Connector J19 Table 7-8. MCPN750A Debug Connector J19 Continued Table 7-8. MCPN750A Debug Connector J19 Continued Table 7-8. MCPN750A Debug Connector J19 Continued MCPN750A Processor RISCWatch Debug Connector J6 Table 7-9. MCPN750A RISCWatch Debug Connector J6TMCPN710 Transition Module CompactPCI Connectors J3/J4/J5 TMCPN710 Transition ModuleTMCPN710 Transition Module COM1 Connector J6 Table 7-10. TMCPN710 COM1 Connector J6TMCPN710 Transition Module COM3 Header J11 TMCPN710 Transition Module COM2 Connector J8Table 7-11. TMCPN710 COM2 Connector J8 Table 7-12. TMCPN710 COM3/COM4 HeadersTable 7-12. TMCPN710 COM3/COM4 Headers TMCPN710 Transition Module COM4 Header J14Same as above TMCPN710 Transition Module 10BaseT/100BaseTx Connector J13 Table 7-13. TMCPN710 10BaseT/100BaseTx Connector J13Table 7-14. TMCPN710 USB 0 Connector J10 TMCPN710 Transition Module USB Connectors J10, J12TMCPN710TransitionModuleIDECompactFLASHConnectors J15, J16 Table 7-15. TMCPN710 USB 1 Connector J12Table 7-16. TMCPN710 Compact FLASH IDE Connectors TMCPN710 Transition Module PMC I/O Connectors J1/J2 Table 7-17. TMCPN710 PMC 1 and 2 I/O ConnectorSignal Table 7-17. TMCPN710 PMC 1 and 2 I/O ConnectorSignal TM-PIMC-0001 CompactPCI User I/O Connector J3, J4, & J5 TM-PIMC-0001 Transition ModuleTM-PIMC-0001 Transition Module COM1 Connector J9 Table 7-18. TM-PIMC-0001 COM1 Connector J9TM-PIMC-0001 Transition Module COM2 Connector J8 Table 7-19. TM-PIMC-0001 COM2 Connector J8TM-PIMC-0001 Transition Module COM3 and COM4 Connectors J12 & J13 Table 7-20. TM-PIMC-0001 COM3 and COM4 HeadersTM-PIMC-0001 Transition Module IDE Compact FLASH Connector J1 TM-PIMC-0001 Transition Module 10BaseT/100BaseTx Connector J7Table 7-21. TM-PIMC-0001 10BaseT/100BaseTx Connector J7 Table 7-22. TM-PIMC-0001 CompactFLASH IDE Connector J1 Connector Pin Assignments Table 7-23. TM-PIMC-0001 PMC I/O Module 1 PIM1 - Host I/OConnector Pin Assignments Connector Pin Assignments ContinuedTable 7-24. TM-PIMC-0001 PMC I/O Module 2 PIM2 - Host I/O Table 7-23. TM-PIMC-0001 PMC I/O Module 1 PIM1 - Host I/ONote PMC I/O modules only use power, ground and the OUT-going serial port pins on the Host I/O connectors. With certain modifications, it is possible for a host I/O module to use all pins except the OUT-going serial port Connector Pin Assignments ContinuedTable 7-24. TM-PIMC-0001 PMC I/O Module 2 PIM2 - Host I/O Table 7-25. PMC I/O Modules 1 and 2 PIM1 and PIM2 PMC I/O Connector Pin AssignmentsJ14/J24 Table 7-25. PMC I/O Modules 1 and 2 PIM1 and PIM2 PMC I/O Connector Pin Assignments ContinuedPMC IO55 7-38 Connector Pin AssignmentsComputer Group Literature Center Web Site Specifications ASpecificationsTable A-1. MCPN750A Specifications Cooling Requirements EMC Compliance Specifications Computer Group Literature Center Web SiteMotorola Computer Group Documents BRelated DocumentationTable B-1. Motorola Computer Group Documents Manufacturers’ Documents Table B-2. Manufacturers’ Documentshttp//developer.intel.com/design/bridge/datashts Table B-2. Manufacturers’ Documents Continuedhttp//developer.intel.com/design/network/manuals/278074.htm http//eu.st.com/stonline/index.shtmlRelated Specifications Table B-3. Related SpecificationsTable B-3. Related Specifications Continued Related SpecificationsTable B-3. Related Specifications Continued Index NumericsI N D E I N D E I N D E IN-4I N D E I N D E IN-6I N D E I N D E IN-8I N D E X IN-9I N D E X IN-10