Installation and Use
MCPN750A CompactPCI Single Board Computer
MCPN750A/IH5
September 2001 Edition
Copyright 2001 Motorola, Inc All Rights Reserved
Printed in the United States of America
Safety Summary
Use Caution When Exposing or Handling a CRT
Ground the Instrument
Do Not Operate in an Explosive Atmosphere
Lithium Battery Caution
Flammability
EMI Caution
instructions
CE Notice European Community
Limited and Restricted Rights Legend
CHAPTER 1 Hardware Preparation and Installation
Contents
About This Manual
CHAPTER 2 Startup and Operation
CHAPTER 3 PPCBug
CHAPTER 5 Remote Start Via the PCI Bus
CHAPTER 4 CNFG and ENV Commands
CHAPTER 6 Functional Description
CHAPTER 7 Connector Pin Assignments
Specifications
APPENDIX A
APPENDIX B
Related Documentation
Page
List of Figures
Page
List of Tables
Table 7-25. PMC I/O Modules 1 and 2 PIM1 and PIM2
About This Manual
Currently, the boards are provided in the following configurations
Overview of Contents
Summary of Changes
Date
Changes
Comments and Suggestions
Conventions Used in This Manual
bold
Enter, Return or CR
CTRL
Hardware Preparation and Installation
Block Diagram
Introduction
Product Description
Figure 1-1. MCPN750A Baseboard Block Diagram
Debug Connector
33MHz 32/64-bit PCI Local Bus
33MHz 32/64-bit CompactPCI Bus
Getting Started
Overview of Start-up Procedure
Table 1-1. Startup Overview
Equipment Required
Table 1-1. Startup Overview Continued
ESD Precautions
Unpacking Instructions
Preparation
Hardware Configuration
MCPN750A Baseboard Preparation
Flash Bank Selection J7
Preparation
Stand-Alone Operating Mode J8
Fuses,Connectors,Headers,MCPN750AFigure 1-2.Switches
LEDs
2703
System Considerations
TMCPN710 Transition Module Preparation
Figure 1-3. TMCPN710 Connector and Header Locations
Hardware Preparation and Installation
1-12
Computer Group Literature Center Web Site
Serial Ports 1 and
Figure 1-4. MCPN750A/TMCPN710 Serial Ports 1 and
MCPN750A
RJ45
TMCPN710
COM3 and COM4 Asynchronous Serial Ports
Figure 1-5. TMCPN710 Serial Ports 3 and
MCPN750A
TMCPN710
TM-PIMC-0001 Transition Module Preparation
Figure 1-6. TM-PIMC-0001
Connector and Header Locations
2694
COM1 and COM2 Asynchronous Serial Ports
Figure 1-7. MCPN750A/TM-PIMC-0001 Serial Ports 1 and
MCPN750
TM-PIMC-0001
RJ45
The signals for COM3 and COM4 serial ports are routed to 10-pin headers on the TM-PIMC-0001 Transition Module J12 and J13. These headers function as I/O connectors for the MCPN750A and are permanently configured as DTE. Figure 1-8 depicts this configuration
Figure 1-8. TM-PIMC-0001 Serial Ports 3 and
COM3 and COM4 Asynchronous Serial Ports
Hardware Installation
Installing PMC Modules on the MCPN750A SBC
Figure 1-9. PMC Module Placement on MCPN750A
5. Remove the PMC filler from the front panel of the MCPN750A
Installing the MCPN750A Baseboard
Hardware Installation
Installing a TMCPN710 or TM-PIMC-0001 Transition Module
Installing PIMs on the TM-PIMC-0001 Transition Module
Figure 1-10. Installing a PIM on the TM-PIMC-0001 Transition Module
Installing the Transition Module in the Chassis
Dangerous voltages, capable of causing death, are present in
Figure 1-11. TMCPN710 or TM-PIMC-0001/MCPN750A Mating Configuration
Hardware Preparation and Installation
1-30
Computer Group Literature Center Web Site
Voltage
MCPN750A Module Power Requirements
Current Available to PMCs & Transition Modules
1-32
Hardware Preparation and Installation
Computer Group Literature Center Web Site
Startup and Operation
Applying Power
Introduction
IF ENABLED AUTOBOOT IF ENABLED OPERATING SYSTEM
Figure 2-1. PPCBug System Startup
STARTUP SYSTEM INITIALIZATION CONSOLE DETECTION RUN SELFTESTS
Default Processor Memory Map
Table 2-1. Processor Default View of the Memory Map
Memory Maps
Processor Memory Map
Table 2-1. Processor Default View of the Memory Map Continued
PCI Local Bus Memory Map
CompactPCI Memory Map
Address Decoding with the
L2 Cache
System Clock Generator
PPC Bus Arbitration
PCI Host Bridge
supported. The Raven supports PowerPC processor external bus frequencies up to 66 MHz and PCI frequencies up to 33 MHz. The Raven is connected to the processor data parity signals to provide processor data bus parity generation and checking
PCI Arbitration
Interrupt Handling
Sources of Reset
ISA DMA Channels
Table 2-2. Classes of Reset and Effectiveness
Power-On Reset
Undervoltage Reset
Front Panel Push Button Reset
CompactPCI Reset RST#
Endian Issues
Software Resets
Reset Source Identification
Processor/Memory Domain
PCI Domain
Role of the Raven ASIC
PCI and Ethernet
2-14
Startup and Operation
Computer Group Literature Center Web Site
PPCBug Overview
PPCBug
PPCBug Basics
Breakpoint and tracing capabilities
Memory Requirements
MPU, Hardware, and Firmware Initialization
PPCBug Implementation
7. Calculate the external bus clock speed of the MPU
Using PPCBug
Debugger Commands
Table 3-1. Debugger Commands
Command
Table 3-1. Debugger Commands Continued
Description
Command
Table 3-1. Debugger Commands Continued
Description
Diagnostic Tests
Table 3-1. Debugger Commands Continued
Table 3-2. Diagnostic Test Groups
Notes You may enter command names in either uppercase or lowercase
MCPN750A, unless SCSI or Video PMCs are installed
Test Sets marked with an asterisk * are not available on the
PPCBug
CNFG and ENV Commands
Overview
CNFG - Configure Board Information Block
Configuring the PPCBug Parameters
ENV - Set Environment
Auto-Initialize of NVRAM Header Enable Y/N = Y?
Network PReP-Boot Mode Enable Y/N = N?
SCSI Bus Reset on Debugger Startup Y/N = N?
Primary SCSI Bus Negotiations Type A/S/N = A?
NVRAM Bootlist GEV.fw-boot-path Boot Enable Y/N = N?
NVRAM Bootlist GEV.fw-boot-path Boot at power-up only Y/N = N?
NVRAM Bootlist GEV.fw-boot-path Boot Abort Delay = 5?
Auto Boot Enable Y/N = N?
Default = $00
ROM Boot Enable Y/N = N?
ROM Boot at power-up only Y/N = Y?
ROM Boot Abort Delay = 5?
ROM Boot Direct Starting Address = FFF00000?
If you use the NIOT debugger command, these parameters need
The default Starting Address is $00000000
Note This parameter above also applies to enabling ECC for DRAM
seconds
LO, TA, VE
Firmware Command Buffer ‘NULL’ terminates entry?
Overview
Remote Start Via the PCI Bus
Introduction
A command data and result field. This field provides the data, if any, needed by the command and provides the response from PPCBug upon command completion. The meaning of the bits in this field are specific to each command opcode
Command/response Register Description
register description continues
Bits 9 to 15 7 bit command option field. Each command specifies the particular meaning of each of the command option bits. Option bits which are unused are considered reserved and should be written to 0 to ensure compatibility with future implementations of this interface
Opcode 0x01 Write/Read Virtual Register
Opcode 0x02 Initialize Memory
Opcode 0x03 Write/Read Memory
Opcode 0x04 Checksum Memory
Opcode 0x06 Debugger Query
Opcode 0x05 Memory Size Query
Opcode 0x07 Execute Code
Command/Response Channel Error Codes
Table 5-1. Command/Respond Error Codes
Demonstration of the Host Interface
MCPN750A target Console
MCP750 host Console
MCPN750A target Console
Start the program from the host console
MCP750 host Console
MCPN750A target Console
PPC1-Bugm 8000EFC4cr
8000EFC4 08030086? 00008007=cr 8000EFC4 00000007? .cr PPC1-Bug
PPC1-Bug Host wrote 0004 to upper half of VR0
Reference Function sromcrc.c
crcflipped = 1 dbit = crc & 1 crc = 1 crcflipped += dbit
Introduction
crc = crcflipped 0xffffffff return crc & 0xffff
5-14
Remote Start Via the PCI Bus
Computer Group Literature Center Web Site
Features
Table 6-1. MCPN750A Features
Functional Description
Introduction
Table 6-1. MCPN750A Features Continued
General Description
Block Diagram
Figure 6-1. MCPN750A Block Diagram
Debug Connector
33MHz 32/64-bit PCI Local Bus
33MHz 32/64-bit CompactPCI Bus
CompactPCI Bus Interface
Ethernet Interface
PCI Mezzanine Interface
PMC Connectors
Signalling Voltage
Mezzanine Type
Configuration and Status Registers
ISA Bus Devices
Serial EEPROM
Asynchronous Serial Ports
PCI Peripheral Bus Controller PBC
ISA Interface
EIDE Interface
USB Interface
ISA Interrupt Controller
ISA DMA Channels
Real-Time Clock/NVRAM/Watchdog Timer Function
Interval Timers
Replacing Lithium Batteries
Use ESD Wrist Strap
Raven General Purpose Timers
Programmable Timers
Hot Swap Control Circuitry
Raven Watchdog Timers
M48T559 Watchdog Timer
Serial Port Signal Multiplexing
Interval Timers
I/O Signal Multiplexing IOMX
Figure 6-2. Serial Port Signal Multiplexing
IOMX Function
Table 6-2. Multiplexing Sequence of the MX Function
Figure 6-3. MX Signal Timings Signal Descriptions
ABORT ABT/RESET RST Switch S1
Serial Ports Defined
Front Panel Indicators DS1 - DS3
MPC750 Processor
Raven PCI-Host Bridge
Flash Memory
Bank A Flash Programming Enable
JTAG/COP
DRAM Memory
ECC Memory Controller
Compact FLASH Memory Card
TMCPN710 Transition Module
TM-PIMC-0001
One standard 50-pin CompactFlash socket for IDE Flash
Functional Description
6-24
Computer Group Literature Center Web Site
Connector Pin Assignments
MCPN750A and Transition Module Connectors
MCPN750A CompactPCI Bus Connectors J1/J2
MCPN750A Connector Pin Assignments
Table 7-1. MCPN750A J1 CompactPCI Connector
Table 7-1. MCPN750A J1 CompactPCI Connector Continued
Table 7-2. MCPN750A J2 CompactPCI Connector
BRSVP2B18
BRSVP2C18
MCPN750A CompactPCI User I/O Connector J3
Table 7-2. MCPN750A J2 CompactPCI Connector Continued
Table 7-3. MCPN750A J3 User I/O Connector
Signal Descriptions
MCPN750A Connector J4
MCPN750A CompactPCI User I/O Connector J5
Table 7-4. MCPN750A J5 User I/O Connector
Signal Descriptions
PMCIO PMC2IO 164 - PMC 2 I/O signals 1 through
MCPN750A PCI Mezzanine Card Connectors J11/21, J12/22, J13/23, J14/24
Table 7-5. MCPN750A PCI Mezzanine Card Connector
Table 7-5. MCPN750A PCI Mezzanine Card Connector Continued
Table 7-6. MCPN750A PCI Mezzanine Card Connector
Table 7-6. MCPN750A PCI Mezzanine Card Connector Continued
MCPN750A Debug Connector J19
MCPN750A 10BaseT/100BaseTx Connector J18
Table 7-7. MCPN750A 10BaseT/100BaseTx Connector J18
Table 7-8. MCPN750A Debug Connector J19
Table 7-8. MCPN750A Debug Connector J19 Continued
Table 7-8. MCPN750A Debug Connector J19 Continued
Table 7-8. MCPN750A Debug Connector J19 Continued
MCPN750A Processor RISCWatch Debug Connector J6
Table 7-9. MCPN750A RISCWatch Debug Connector J6
TMCPN710 Transition Module CompactPCI Connectors J3/J4/J5
TMCPN710 Transition Module
TMCPN710 Transition Module COM1 Connector J6
Table 7-10. TMCPN710 COM1 Connector J6
TMCPN710 Transition Module COM2 Connector J8
Table 7-11. TMCPN710 COM2 Connector J8
TMCPN710 Transition Module COM3 Header J11
Table 7-12. TMCPN710 COM3/COM4 Headers
Table 7-12. TMCPN710 COM3/COM4 Headers
TMCPN710 Transition Module COM4 Header J14
Same as above
TMCPN710 Transition Module 10BaseT/100BaseTx Connector J13
Table 7-13. TMCPN710 10BaseT/100BaseTx Connector J13
TMCPN710 Transition Module USB Connectors J10, J12
TMCPN710TransitionModuleIDECompactFLASHConnectors J15, J16
Table 7-14. TMCPN710 USB 0 Connector J10
Table 7-15. TMCPN710 USB 1 Connector J12
Table 7-16. TMCPN710 Compact FLASH IDE Connectors
TMCPN710 Transition Module PMC I/O Connectors J1/J2
Table 7-17. TMCPN710 PMC 1 and 2 I/O Connector
Signal
Table 7-17. TMCPN710 PMC 1 and 2 I/O Connector
Signal
TM-PIMC-0001 CompactPCI User I/O Connector J3, J4, & J5
TM-PIMC-0001 Transition Module
TM-PIMC-0001 Transition Module COM1 Connector J9
Table 7-18. TM-PIMC-0001 COM1 Connector J9
TM-PIMC-0001 Transition Module COM2 Connector J8
Table 7-19. TM-PIMC-0001 COM2 Connector J8
TM-PIMC-0001 Transition Module COM3 and COM4 Connectors J12 & J13
Table 7-20. TM-PIMC-0001 COM3 and COM4 Headers
TM-PIMC-0001 Transition Module IDE Compact FLASH Connector J1
TM-PIMC-0001 Transition Module 10BaseT/100BaseTx Connector J7
Table 7-21. TM-PIMC-0001 10BaseT/100BaseTx Connector J7
Table 7-22. TM-PIMC-0001 CompactFLASH IDE Connector J1
Connector Pin Assignments
Table 7-23. TM-PIMC-0001 PMC I/O Module 1 PIM1 - Host I/O
Connector Pin Assignments Continued
Table 7-24. TM-PIMC-0001 PMC I/O Module 2 PIM2 - Host I/O
Connector Pin Assignments
Table 7-23. TM-PIMC-0001 PMC I/O Module 1 PIM1 - Host I/O
Note PMC I/O modules only use power, ground and the OUT-going serial port pins on the Host I/O connectors. With certain modifications, it is possible for a host I/O module to use all pins except the OUT-going serial port
Connector Pin Assignments Continued
Table 7-24. TM-PIMC-0001 PMC I/O Module 2 PIM2 - Host I/O
Table 7-25. PMC I/O Modules 1 and 2 PIM1 and PIM2
PMC I/O Connector Pin Assignments
J14/J24
Table 7-25. PMC I/O Modules 1 and 2 PIM1 and PIM2
PMC I/O Connector Pin Assignments Continued
PMC IO55
7-38
Connector Pin Assignments
Computer Group Literature Center Web Site
Specifications
ASpecifications
Table A-1. MCPN750A Specifications
Cooling Requirements
EMC Compliance
Specifications
Computer Group Literature Center Web Site
Motorola Computer Group Documents
BRelated Documentation
Table B-1. Motorola Computer Group Documents
Manufacturers’ Documents
Table B-2. Manufacturers’ Documents
Table B-2. Manufacturers’ Documents Continued
http//developer.intel.com/design/network/manuals/278074.htm
http//developer.intel.com/design/bridge/datashts
http//eu.st.com/stonline/index.shtml
Related Specifications
Table B-3. Related Specifications
Table B-3. Related Specifications Continued
Related Specifications
Table B-3. Related Specifications Continued
Index
Numerics
I N D E
I N D E
I N D E
IN-4
I N D E
I N D E
IN-6
I N D E
I N D E
IN-8
I N D E X
IN-9
I N D E X
IN-10
