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Motorola IH5 manual MCPN750A Processor RISCWatch Debug Connector J6

Models: IH5 MCPN750A

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MCPN750A Processor RISCWatch Debug Connector (J6)

MCPN750A Connector Pin Assignments

MCPN750A Processor RISCWatch Debug Connector (J6)

A 15-pin header (J6) provides access to the Processor RISCWatch JTAG/COP interface. The pin assignments are listed in the following table.

Table 7-9. MCPN750A RISCWatch Debug Connector (J6)

1	TDO	No Connect	2
3			4
3	TDI	TRST-L	4
5			6
5	No Connect	Pullup	6
7			8
7	TCK	No Connect	8
9			10
9	TMS	No Connect	10
11			12
11	SRESET_L	No Connect	12
13			14
13	CPU RESET_L	No Pin	14
15			16
15	CKSTPO_L	GND	16

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Motorola IH5 manual MCPN750A Processor RISCWatch Debug Connector J6, 9. MCPN750A RISCWatch Debug Connector J6

Contents

MCPN750A CompactPCI Single Board Computer Installation and UseMCPN750A/IH5 September 2001 EditionPrinted in the United States of America Copyright 2001 Motorola, Inc All Rights ReservedUse Caution When Exposing or Handling a CRT Safety SummaryGround the Instrument Do Not Operate in an Explosive AtmosphereFlammability Lithium Battery CautionEMI Caution instructionsCE Notice European Community Limited and Restricted Rights Legend CHAPTER 1 Hardware Preparation and Installation ContentsAbout This Manual CHAPTER 3 PPCBug CHAPTER 2 Startup and OperationCHAPTER 5 Remote Start Via the PCI Bus CHAPTER 4 CNFG and ENV CommandsCHAPTER 6 Functional Description CHAPTER 7 Connector Pin Assignments APPENDIX A SpecificationsAPPENDIX B Related DocumentationPage List of Figures Page List of Tables Table 7-25. PMC I/O Modules 1 and 2 PIM1 and PIM2 Currently, the boards are provided in the following configurations About This ManualSummary of Changes Overview of ContentsDate ChangesComments and Suggestions bold Conventions Used in This ManualEnter, Return or CR CTRLBlock Diagram Hardware Preparation and InstallationIntroduction Product DescriptionDebug Connector Figure 1-1. MCPN750A Baseboard Block Diagram33MHz 32/64-bit PCI Local Bus 33MHz 32/64-bit CompactPCI BusGetting Started Overview of Start-up ProcedureTable 1-1. Startup Overview Table 1-1. Startup Overview Continued Equipment RequiredUnpacking Instructions ESD PrecautionsPreparation Hardware ConfigurationMCPN750A Baseboard Preparation Preparation Flash Bank Selection J7Stand-Alone Operating Mode J8 Fuses,Connectors,Headers,MCPN750AFigure 1-2.Switches LEDs2703 System Considerations TMCPN710 Transition Module Preparation Hardware Preparation and Installation Figure 1-3. TMCPN710 Connector and Header Locations1-12 Computer Group Literature Center Web SiteSerial Ports 1 and MCPN750A Figure 1-4. MCPN750A/TMCPN710 Serial Ports 1 andRJ45 TMCPN710Figure 1-5. TMCPN710 Serial Ports 3 and COM3 and COM4 Asynchronous Serial PortsMCPN750A TMCPN710TM-PIMC-0001 Transition Module Preparation Figure 1-6. TM-PIMC-0001 Connector and Header Locations2694 COM1 and COM2 Asynchronous Serial Ports MCPN750 Figure 1-7. MCPN750A/TM-PIMC-0001 Serial Ports 1 andTM-PIMC-0001 RJ45The signals for COM3 and COM4 serial ports are routed to 10-pin headers on the TM-PIMC-0001 Transition Module J12 and J13. These headers function as I/O connectors for the MCPN750A and are permanently configured as DTE. Figure 1-8 depicts this configuration Figure 1-8. TM-PIMC-0001 Serial Ports 3 andCOM3 and COM4 Asynchronous Serial Ports Installing PMC Modules on the MCPN750A SBC Hardware InstallationFigure 1-9. PMC Module Placement on MCPN750A 5. Remove the PMC filler from the front panel of the MCPN750A Installing the MCPN750A Baseboard Hardware Installation Installing PIMs on the TM-PIMC-0001 Transition Module Installing a TMCPN710 or TM-PIMC-0001 Transition ModuleFigure 1-10. Installing a PIM on the TM-PIMC-0001 Transition Module Installing the Transition Module in the Chassis Dangerous voltages, capable of causing death, are present in Hardware Preparation and Installation Figure 1-11. TMCPN710 or TM-PIMC-0001/MCPN750A Mating Configuration1-30 Computer Group Literature Center Web SiteVoltage MCPN750A Module Power RequirementsCurrent Available to PMCs & Transition Modules 1-32 Hardware Preparation and InstallationComputer Group Literature Center Web Site Startup and Operation Applying PowerIntroduction IF ENABLED AUTOBOOT IF ENABLED OPERATING SYSTEM Figure 2-1. PPCBug System StartupSTARTUP SYSTEM INITIALIZATION CONSOLE DETECTION RUN SELFTESTS Table 2-1. Processor Default View of the Memory Map Default Processor Memory MapMemory Maps Processor Memory MapPCI Local Bus Memory Map Table 2-1. Processor Default View of the Memory Map ContinuedAddress Decoding with the CompactPCI Memory MapSystem Clock Generator L2 CachePPC Bus Arbitration PCI Host Bridgesupported. The Raven supports PowerPC processor external bus frequencies up to 66 MHz and PCI frequencies up to 33 MHz. The Raven is connected to the processor data parity signals to provide processor data bus parity generation and checking Interrupt Handling PCI ArbitrationISA DMA Channels Sources of ResetTable 2-2. Classes of Reset and Effectiveness Undervoltage Reset Power-On ResetFront Panel Push Button Reset CompactPCI Reset RST#Software Resets Endian IssuesReset Source Identification Processor/Memory DomainPCI Domain Role of the Raven ASICPCI and Ethernet 2-14 Startup and OperationComputer Group Literature Center Web Site PPCBug Overview PPCBugPPCBug Basics Breakpoint and tracing capabilities Memory Requirements MPU, Hardware, and Firmware InitializationPPCBug Implementation 7. Calculate the external bus clock speed of the MPU Using PPCBug Debugger Commands Table 3-1. Debugger Commands Command Table 3-1. Debugger Commands ContinuedDescription Command Table 3-1. Debugger Commands ContinuedDescription Table 3-1. Debugger Commands Continued Diagnostic TestsTable 3-2. Diagnostic Test Groups MCPN750A, unless SCSI or Video PMCs are installed Notes You may enter command names in either uppercase or lowercaseTest Sets marked with an asterisk * are not available on the PPCBugOverview CNFG and ENV CommandsCNFG - Configure Board Information Block ENV - Set Environment Configuring the PPCBug ParametersNetwork PReP-Boot Mode Enable Y/N = N? Auto-Initialize of NVRAM Header Enable Y/N = Y?SCSI Bus Reset on Debugger Startup Y/N = N? Primary SCSI Bus Negotiations Type A/S/N = A?NVRAM Bootlist GEV.fw-boot-path Boot at power-up only Y/N = N? NVRAM Bootlist GEV.fw-boot-path Boot Enable Y/N = N?NVRAM Bootlist GEV.fw-boot-path Boot Abort Delay = 5? Auto Boot Enable Y/N = N?Default = $00 ROM Boot at power-up only Y/N = Y? ROM Boot Enable Y/N = N?ROM Boot Abort Delay = 5? ROM Boot Direct Starting Address = FFF00000?If you use the NIOT debugger command, these parameters need The default Starting Address is $00000000 Note This parameter above also applies to enabling ECC for DRAM seconds Firmware Command Buffer ‘NULL’ terminates entry? LO, TA, VEOverview Remote Start Via the PCI BusIntroduction A command data and result field. This field provides the data, if any, needed by the command and provides the response from PPCBug upon command completion. The meaning of the bits in this field are specific to each command opcode register description continues Command/response Register DescriptionBits 9 to 15 7 bit command option field. Each command specifies the particular meaning of each of the command option bits. Option bits which are unused are considered reserved and should be written to 0 to ensure compatibility with future implementations of this interface Opcode 0x02 Initialize Memory Opcode 0x01 Write/Read Virtual RegisterOpcode 0x04 Checksum Memory Opcode 0x03 Write/Read MemoryOpcode 0x06 Debugger Query Opcode 0x05 Memory Size QueryOpcode 0x07 Execute Code Table 5-1. Command/Respond Error Codes Command/Response Channel Error CodesMCPN750A target Console Demonstration of the Host InterfaceMCPN750A target Console MCP750 host ConsoleStart the program from the host console MCP750 host ConsolePPC1-Bugm 8000EFC4cr MCPN750A target Console8000EFC4 08030086? 00008007=cr 8000EFC4 00000007? .cr PPC1-Bug PPC1-Bug Host wrote 0004 to upper half of VR0Reference Function sromcrc.c crcflipped = 1 dbit = crc & 1 crc = 1 crcflipped += dbit Introductioncrc = crcflipped 0xffffffff return crc & 0xffff 5-14 Remote Start Via the PCI BusComputer Group Literature Center Web Site Table 6-1. MCPN750A Features FeaturesFunctional Description IntroductionGeneral Description Table 6-1. MCPN750A Features ContinuedBlock Diagram Debug Connector Figure 6-1. MCPN750A Block Diagram33MHz 32/64-bit PCI Local Bus 33MHz 32/64-bit CompactPCI BusCompactPCI Bus Interface Ethernet Interface PMC Connectors PCI Mezzanine InterfaceSignalling Voltage Mezzanine TypeISA Bus Devices Configuration and Status RegistersSerial EEPROM Asynchronous Serial PortsISA Interface PCI Peripheral Bus Controller PBCUSB Interface EIDE InterfaceISA Interrupt Controller ISA DMA ChannelsInterval Timers Real-Time Clock/NVRAM/Watchdog Timer FunctionReplacing Lithium Batteries Use ESD Wrist Strap Raven General Purpose Timers Programmable TimersHot Swap Control Circuitry M48T559 Watchdog Timer Raven Watchdog TimersInterval Timers Serial Port Signal MultiplexingI/O Signal Multiplexing IOMX Figure 6-2. Serial Port Signal MultiplexingIOMX Function Table 6-2. Multiplexing Sequence of the MX Function Figure 6-3. MX Signal Timings Signal Descriptions ABORT ABT/RESET RST Switch S1Serial Ports Defined MPC750 Processor Front Panel Indicators DS1 - DS3Raven PCI-Host Bridge Flash MemoryJTAG/COP Bank A Flash Programming EnableDRAM Memory ECC Memory ControllerCompact FLASH Memory Card TM-PIMC-0001 TMCPN710 Transition ModuleFunctional Description One standard 50-pin CompactFlash socket for IDE Flash6-24 Computer Group Literature Center Web SiteMCPN750A and Transition Module Connectors Connector Pin AssignmentsMCPN750A CompactPCI Bus Connectors J1/J2 MCPN750A Connector Pin AssignmentsTable 7-1. MCPN750A J1 CompactPCI Connector Table 7-2. MCPN750A J2 CompactPCI Connector Table 7-1. MCPN750A J1 CompactPCI Connector ContinuedBRSVP2B18 BRSVP2C18Table 7-2. MCPN750A J2 CompactPCI Connector Continued MCPN750A CompactPCI User I/O Connector J3Signal Descriptions Table 7-3. MCPN750A J3 User I/O ConnectorMCPN750A Connector J4 Table 7-4. MCPN750A J5 User I/O Connector MCPN750A CompactPCI User I/O Connector J5PMCIO PMC2IO 164 - PMC 2 I/O signals 1 through Signal DescriptionsTable 7-5. MCPN750A PCI Mezzanine Card Connector MCPN750A PCI Mezzanine Card Connectors J11/21, J12/22, J13/23, J14/24Table 7-6. MCPN750A PCI Mezzanine Card Connector Table 7-5. MCPN750A PCI Mezzanine Card Connector ContinuedTable 7-6. MCPN750A PCI Mezzanine Card Connector Continued MCPN750A Debug Connector J19 MCPN750A 10BaseT/100BaseTx Connector J18Table 7-7. MCPN750A 10BaseT/100BaseTx Connector J18 Table 7-8. MCPN750A Debug Connector J19 Table 7-8. MCPN750A Debug Connector J19 Continued Table 7-8. MCPN750A Debug Connector J19 Continued Table 7-8. MCPN750A Debug Connector J19 Continued Table 7-9. MCPN750A RISCWatch Debug Connector J6 MCPN750A Processor RISCWatch Debug Connector J6TMCPN710 Transition Module TMCPN710 Transition Module CompactPCI Connectors J3/J4/J5Table 7-10. TMCPN710 COM1 Connector J6 TMCPN710 Transition Module COM1 Connector J6Table 7-11. TMCPN710 COM2 Connector J8 TMCPN710 Transition Module COM2 Connector J8TMCPN710 Transition Module COM3 Header J11 Table 7-12. TMCPN710 COM3/COM4 HeadersTable 7-12. TMCPN710 COM3/COM4 Headers TMCPN710 Transition Module COM4 Header J14Same as above Table 7-13. TMCPN710 10BaseT/100BaseTx Connector J13 TMCPN710 Transition Module 10BaseT/100BaseTx Connector J13TMCPN710TransitionModuleIDECompactFLASHConnectors J15, J16 TMCPN710 Transition Module USB Connectors J10, J12Table 7-14. TMCPN710 USB 0 Connector J10 Table 7-15. TMCPN710 USB 1 Connector J12Table 7-16. TMCPN710 Compact FLASH IDE Connectors Table 7-17. TMCPN710 PMC 1 and 2 I/O Connector TMCPN710 Transition Module PMC I/O Connectors J1/J2Signal Table 7-17. TMCPN710 PMC 1 and 2 I/O ConnectorSignal TM-PIMC-0001 Transition Module TM-PIMC-0001 CompactPCI User I/O Connector J3, J4, & J5Table 7-18. TM-PIMC-0001 COM1 Connector J9 TM-PIMC-0001 Transition Module COM1 Connector J9Table 7-19. TM-PIMC-0001 COM2 Connector J8 TM-PIMC-0001 Transition Module COM2 Connector J8Table 7-20. TM-PIMC-0001 COM3 and COM4 Headers TM-PIMC-0001 Transition Module COM3 and COM4 Connectors J12 & J13TM-PIMC-0001 Transition Module IDE Compact FLASH Connector J1 TM-PIMC-0001 Transition Module 10BaseT/100BaseTx Connector J7Table 7-21. TM-PIMC-0001 10BaseT/100BaseTx Connector J7 Table 7-22. TM-PIMC-0001 CompactFLASH IDE Connector J1 Table 7-23. TM-PIMC-0001 PMC I/O Module 1 PIM1 - Host I/O Connector Pin AssignmentsTable 7-24. TM-PIMC-0001 PMC I/O Module 2 PIM2 - Host I/O Connector Pin Assignments ContinuedConnector Pin Assignments Table 7-23. TM-PIMC-0001 PMC I/O Module 1 PIM1 - Host I/ONote PMC I/O modules only use power, ground and the OUT-going serial port pins on the Host I/O connectors. With certain modifications, it is possible for a host I/O module to use all pins except the OUT-going serial port Connector Pin Assignments ContinuedTable 7-24. TM-PIMC-0001 PMC I/O Module 2 PIM2 - Host I/O Table 7-25. PMC I/O Modules 1 and 2 PIM1 and PIM2 PMC I/O Connector Pin AssignmentsJ14/J24 Table 7-25. PMC I/O Modules 1 and 2 PIM1 and PIM2 PMC I/O Connector Pin Assignments ContinuedPMC IO55 7-38 Connector Pin AssignmentsComputer Group Literature Center Web Site Specifications ASpecificationsTable A-1. MCPN750A Specifications Cooling Requirements EMC Compliance Computer Group Literature Center Web Site SpecificationsMotorola Computer Group Documents BRelated DocumentationTable B-1. Motorola Computer Group Documents Table B-2. Manufacturers’ Documents Manufacturers’ Documentshttp//developer.intel.com/design/network/manuals/278074.htm Table B-2. Manufacturers’ Documents Continuedhttp//developer.intel.com/design/bridge/datashts http//eu.st.com/stonline/index.shtmlTable B-3. Related Specifications Related SpecificationsRelated Specifications Table B-3. Related Specifications ContinuedTable B-3. Related Specifications Continued Numerics IndexI N D E I N D E IN-4 I N D EI N D E IN-6 I N D EI N D E IN-8 I N D EIN-9 I N D E XIN-10 I N D E X