1

Hardware Preparation and Installation

Arbitration

Control

L2 Cache

1M

Processor MPC750

Core Power

Debug Connector

66MHz PPC603 Processor Bus

Memory

Controller

Falcon 3

Chipset

PCI Bridge

&MPIC

Raven 5 ASIC

DRAM

 

DRAM

(Bank 1)

 

(Bank 2)

16M/64M/128M

 

16M/64M/128M

 

 

Flash

 

 

(soldered)

 

 

4M

SROM

 

Flash

AT24C04

 

(socketed)

 

 

1M

Interrupt

 

System

 

Registers

Serializer

 

 

Clock

Reset

Hot Swap

Generator

Control

Control

33MHz 32/64-bit PCI Local Bus

Ethernet

PBC

PCI-PCI BRIDGE

Intel 21143

VT82C586B

Intel 21554

Ethernet

Serial

PMC Slot 1 PMC Slot 2

 

 

 

ISA

 

 

 

10BT/

 

Registers

 

 

ISA

 

USB0

USB1

EIDE

100BTx

 

 

 

 

 

 

 

 

 

NVRAM/

 

 

 

 

 

 

WD/RTC

 

 

 

RS232

 

MK48T559

 

 

 

 

 

 

 

 

 

 

 

UARTs

 

 

 

TO TM)

 

 

16C550C

 

 

 

 

1SERIAL 2SERIAL 3SERIAL

4SERIAL

 

 

ROUTING(OPTIONAL

IOMX

 

 

 

 

 

 

 

 

 

 

User I/O J3 & J5

 

 

 

 

33MHz 32/64-bit CompactPCI Bus

CompactPCI J1/J2

Figure 1-1. MCPN750A Baseboard Block Diagram

1-2

Computer Group Literature Center Web Site

Page 22
Image 22
Motorola IH5 manual MCPN750A Baseboard Block Diagram