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PMC-Sierra PM5349 manual Sdins, Sfins, Lofins, Losins

Models: PM5349

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		PMC-Sierra, Inc.	PM5349 S/UNI-QUAD
S/UNI-QUAD			PM5349 S/UNI-QUAD
S/UNI-QUAD
DATASHEET


PMC-971239	ISSUE 6		SATURN USER NETWORK INTERFACE (155-QUAD)

Register 0x94: S/UNI-QUAD Channel Receive Line AIS Control

Bit	Type	Function	Default
Bit 7	R/W	SDINS	0
Bit 6	R/W	SFINS	0
Bit 5	R/W	LOFINS	1
Bit 4	R/W	LOSINS	1
Bit 3	R/W	Reserved	0
Bit 2	R/W	Reserved	0
Bit 1		Unused	X
Bit 0	R/W	Reserved	0

LOSINS:

This bit is active only when the ALLONES bit in the RLOP Control/Status register is set high; it is ignored if the ALLONES bit is set low. The LOSINS bit enables the insertion of line AIS in the receive direction upon the declaration of loss of signal (LOS). If LOSINS is a logic one, line AIS is inserted into the SONET/SDH frame when LOS is declared. Line AIS is terminated when LOS is removed.

LOFINS:

This bit is active only when the ALLONES bit in the RLOP Control/Status register is set high; it is ignored if the ALLONES bit is set low. The LOFINS bit enables the insertion of line AIS in the receive direction upon the declaration of loss of frame (LOF). If LOSINS is a logic one, line AIS is inserted into the SONET/SDH frame when LOS is declared. Line AIS is terminated when LOS is removed.

SFINS:

This bit is active only when the ALLONES bit in the RLOP Control/Status register is set high; it is ignored if the ALLONES bit is set low. The SFINS bit enables the insertion of line AIS in the receive direction upon the declaration of signal fail (SF). If SFINS is a logic one, line AIS is inserted into the SONET/SDH frame when SF is declared. Line AIS is terminated when SF is removed.

SDINS:

This bit is active only when the ALLONES bit in the RLOP Control/Status register is set high; it is ignored if the ALLONES bit is set low. The SDINS bit enables the insertion of line AIS in the receive direction upon the declaration of signal degrade (SD). If SDINS is a logic one, line AIS is inserted into the

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PMC-Sierra PM5349 manual Sdins, Sfins, Lofins, Losins

Contents

UNI-QUAD Saturn User Network Interface Issue Issue Date Details of Change Revision HistoryContents Receive Line Overhead Processor Rlop Transmit ATM Cell Processor Txcp Analog Power Supply Filtering Sonet Receiver FeaturesGeneral Receive ATM Processor Sonet TransmitterTransmit ATM Processor Applications References Definitions Typical STS-3c STM-1 ATM Switch Port Application Application ExamplesBlock Diagram CS BDescription PM5349 S/UNI-QUAD PIN Diagram Bottom ViewLine Side Interface Signals Pin Name Type Function PIN DescriptionPin Name Type Function Tfpi TclkTfpo TDAT9TDAT8 TDAT7Tprty TsocTenb TADR4TADR3 TADR2TCA TfclkDTCA4 DTCA3DTCA2 DTCA1Renb RprtyRsoc RADR4 RADR3RADR2 RADR1DRCA4 DRCA3DRCA2 DRCA1Microprocessor Interface Signals Pin Name Type Function CSBRDB WRBIntb RstbALE Jtag Test Access Port TAP Signals Pin Name Type Function Analog Signals Pin Name Type Function Power and Ground Pin Name Type FunctionVDD AA3AB2 AC1VSS AA2AB1 AB3 AC2 AC6 AC8Qavd AA6 QAVD1QAVD2 QavsAVS AC3TAVS1A CSU TAVS1B CSU5V tolerant I/O’s TRSTB, TCK, TMS, TDI, TDOReceive Line Interface Crsi Clock RecoveryFunctional Description Framer Serial to Parallel ConverterReceive Section Overhead Processor Rsop Descramble Error MonitorLoss of Signal Error Monitor Block Loss of FrameReceive Line Overhead Processor Rlop Line RDI DetectPM5349 S/UNI-QUAD Bit Error Rate Monitor Synchronization Status ExtractionReceive Path Overhead Processor Rpop Pointer InterpreterLOP AIS Pointer Interpreter Event Indications DescriptionPM5349 S/UNI-QUAD Pointer Interpreter Transition Description SPE Timing Receive ATM Cell Processor Rxcp Cell DelineationDescrambler Cell Filter and HCS VerificationHCS Verification State Diagram Clock Synthesis Performance MonitorTransmit Line Interface Cspi Parallel to Serial Converter Transmit Section Overhead Processor TsopLine AIS Insert BIP-8 InsertFraming and Identity Insert ScramblerTransmit Line Overhead Processor Tlop APS InsertPointer Generator Line Febe InsertTransmit Path Overhead Processor Tpop BIP-8 Calculate Febe CalculateTransmit ATM Cell Processor Txcp Idle/Unassigned Cell GeneratorHCS Generator Utopia Level 2 System InterfaceReceive ATM Interface Transmit ATM InterfaceRegister Memory Map Jtag Test Access PortMicroprocessor Interface REG Address A100 Description Tpop Path Signal Label Rxcp Configuration362 Rxcp FIFO/UTOPIA Control & Config 363 Rxcp Interrupt Enables and Counter StatusTxcp Configuration Txcp Transmit Cell Status/Configuration OptionsTxcp Interrupt Enable/Status Rxcp Idle Cell Count LSB 06F 16F 26F 36F0EF 1EF 2EF 3EF Rase APS K1Rase APS K2 0FB 1FB 2FB 3FBReserved for Test 0FE 1FE 2FE 3FEUNI-QUAD Master Test Register Normal Mode Register Description Reset TYPE3TYPE2 TYPE1Bit Reserved TFPOCH1TFPOCH0 Tfpo Channel SelectionPM5349 S/UNI-QUAD PHYADR2 PHYADR1PHYADR0 PhyenTclka RfclkaTfclka RefclkaRCLK1A RCLK2ARCLK3A RCLK4ACsui CHNL4ICHNL3I CHNL2ICsui Chreset TIPAutopfebe AutolfebeAutolrdi AutoprdiTfpien RxdinvLoopt SdleRxdinv PM5349 S/UNI-QUAD Rasei CruiTxcpi RxcpiTxcpi Troole TrooliTroolv PM5349 S/UNI-QUAD Rrooli RdooliRroolv RdoolvRdooli PM5349 S/UNI-QUAD Bipword FoofALGO2 BipeeDDS Bipei LosiLofi OofiBipei Register 0x13 Rsop Section BIP-8 MSB Bit Type Function DefaultBit SBE7 SBE6 SBE5 SBE4 SBE3 SBE2 SBE1 SBE0 Register 0x14 Tsop Control Bit Type Function Default LaisRegister 0x15 Tsop Diagnostic Bit Type Function Default DlosDBIP8 DFPRegister 0x18 Rlop Control/Status Bit Type Function Default Lrdidet Laise LrdieFebei LaisiFebee Bit LBE15 LBE14 LBE13 LBE12 LBE11 LBE10 LBE9 LBE8 Bit LBE7 LBE6 LBE5 LBE4 LBE3 LBE2 LBE1 LBE0Register 0x1B Rlop Line BIP-24 Register 0x1C Rlop Line BIP-24 MSB Bit Type Function Default Register 0x1D Rlop Line Febe LSB Bit Type Function Default Bit LFE7 LFE6 LFE5 LFE4 LFE3 LFE2 LFE1 LFE0Register 0x1E Rlop Line Febe Bit LFE15 LFE14 LFE13 LFE12 LFE11 LFE10 LFE9 LFE8Register 0x1F Rlop Line Febe MSB Bit Type Function Default Lrdi Register 0x20 Tlop Control Bit Type Function DefaultApsreg Register 0x21 Tlop Diagnostic Bit Type Function Default DbipRegister 0x22 Tlop Transmit K1 Bit Type Function Default Register 0x23 Tlop Transmit K2 Bit Type Function Default PM5349 S/UNI-QUAD Lopconv LopvPaisonv PaisvPaisconv PlopvIinvcnt ERDIV2ERDIV1 ERDIV0Psli LopiPaisi Prdii104 Erdii Illjreqi DiscopaiInvndfi Illptri107 Prdie LopePaise Psle Erdie Illjreqe DiscopaeInvndfe Illptre112 Register 0x35 Rpop Pointer LSB Bit Type Function Default RDI10 NdfporExtd 115 116 Register 0x39 Rpop Path BIP-8 MSB Register 0x38 Rpop Path BIP-8 LSB Bit Type Function DefaultBit PBE7 PBE6 PBE5 PBE4 PBE3 PBE2 PBE1 PBE0 Bit PFE7 PFE6 PFE5 PFE4 PFE3 PFE2 PFE1 PFE0 Register 0x3A Rpop Path Febe LSB Bit Type Function DefaultRegister 0x3B Rpop Path Febe MSB Bit Type Function Default Register 0x3C Rpop Auxiliary RDI Bit Type Function Default AprdieAprdiv Aprdie AprdivSOS EnssBlkbip Blkbipo121 Persist EprdienEprdisrc 123 Ftptr NSEPSE NDF125 CPTR7 CPTR6CPTR5 CPTR4CPTR9 CPTR8APTR7 APTR6APTR5 APTR4APTR8 Bit NDF3 NDF2 NDF1 NDF0APTR9 130 Register 0x49 Tpop Path Status Bit Type Function Default 132 Register 0x60 Rxcp Configuration Bit Type Function Default DiscorHcsadd DdscrRegister 0x61 Rxcp Configuration Bit Type Function Default CcdisHCSFTR1 HCSFTR0Hcspass Rxptyp RcainvFiforst Fiforst RCALEVEL0137 Xferi OVRXfere Fovre139 Oocdi ChcsiUhcsi FovriOocdv LCDC9 LCDC8LCDC7 LCDC6Bit GFC3 GFC2 GFC1 GFC0 PTI3 PTI2 PTI1 CLPMGFC3 MGFC2MGFC1 MGFC0CHCS7 CHCS6CHCS5 CHCS4UHCS7 UHCS6UHCS5 UHCS4RCELL7 RCELL6RCELL5 RCELL4148 ICELL7 ICELL6ICELL5 ICELL4ICELL16 ICELL18ICELL17 Register 0x80 Txcp Configuration Bit Type Function Default TptypDscr HcsbTCALEVEL0 Register 0x81 Txcp Configuration Bit Type Function Default Cell FIFODP1 FIFODP0 Fifo DepthCells H4INSB 156 Tprtye TsoceTprtyi Tsoci158 Bit GFC3 GFC2 GFC1 GFC0 PTI2 PTI1 PTI0 PAYLD7 PAYLD6PAYLD5 PAYLD4Register 0x87 Txcp Transmit Cell Count 162 Sdlrdi SflrdiLoflrdi Loslrdi164 Lcdprdi AlrmprdiPaisprdi Lopprdi166 Lcdeprdi NoalmeprdiNopaiseprdi Pslmeprdi168 Paisconprdi NopaisconeprdiSdins SfinsLofins Losins171 Paisconpais LopconpaisLoppais PaispaisPerdien PrdienPaisen LopenAlarm Description Bit Z1/S1E SdbereSfbere CoapsePsbfi CoapsiSfberi Sdberi177 Sfberten SfsmodeSdberten SdcmodeSfcmode SFSAP7 SFSAP6SFSAP5 SFSAP4SFSAP23 SFSAP22SFSAP21 SFSAP20SFSTH7 SFSTH6SFSTH5 SFSTH4SFDTH7 SFDTH6SFDTH5 SFDTH4SFCTH7 SFCTH6SFCTH5 SFCTH4SDSAP7 SDSAP6SDSAP5 SDSAP4SDSAP23 SDSAP22SDSAP21 SDSAP20SDSTH7 SDSTH6SDSTH5 SDSTH4SDDTH7 SDDTH6SDDTH5 SDDTH4SDCTH7 SDCTH6SDCTH5 SDCTH4Register 0xF5 Rase Receive K1 Bit Type Function Default Register 0xF6 Rase Receive K2 Bit Type Function Default Register 0xF7 Rase Receive Z1/S1 Bit Type Function Default Master Test Register Test Features DescriptionTest Mode Register Memory Map Address Register 0x400 Master Test Bit Type Function Default Pmcatst Test Mode 0 DetailsTest Mode 0 Read Locations Test Mode 0 Write Locations Jtag Test PortExtest Boundary Scan 000Boundary Scan Register Instructions Selected Register Instruction Codes IR20Identification Register MUX Boundary Scan CellsInput Pad Output Cell Outcell Bidirectional Cell IocellPAD Output EnableIocell Operation ATM Mapping into the STS-3c STM-1 SPETransport and Path Overhead Bytes Transport Overhead BytesPath Overhead Bytes ATM Cell Data Structure PAYLOAD1 PAYLOAD2PAYLOAD3 PAYLOAD4 PAYLOAD5 PAYLOAD6205 Recommended Berm settings Clocking OptionsConceptual Clocking Structure Loopback Operation Line Loopback Mode Serial Diagnostic Loopback Mode Parallel Diagnostic Loopback Mode Control Select Tri-state Enable Jtag SupportTDO TMS Trstb TCKTAP Controller TAP Controller Finite State Machine States Test-Logic-Reset Update-DRRun-Test-Idle Capture-DRUpdate-IR Shift-IRBoundary Scan Instructions BypassBoard Design Recommendations IdcodeStctest Power Supply Sequencing Power Sequencing Circuit Analog Power Supply FilteringLAN Mode Analog Power Filters with 3.3V Supply Interfacing to ECL or Pecl DevicesInterfacing to ECL or Pecl Using the S/UNI-QUAD with a 5 Volt ODL Initializing the S/UNI-QUADFunctional Timing ATM Utopia Level 2 System InterfaceMulti-PHY Polling and Addressing Receive Cell Interface 225 Absolute Maximum Ratings Absolute Maximum Ratings16 D.C. Characteristics TBDInput Low Current 100 VIL = GND. Notes 1 Input High Current +10 VIH = VDD. Notes 1Input Low Current +10 VIL = GND. Notes 2 Input High Current +10 VIH = VDD. Notes 2Microprocessor Interface Timing Characteristics Address to Latch Set-up TimeALE CSB+RDB Intb TSALW ALE CSB+WRB TSALW tHALW TV L TSAW tVWR tHAW18 A.C. Timing Characteristics Rstb Pulse Width 100Tfclk Frequency MHz Tfclk Duty CycleTenb Set-up time to Tfclk Tenb Hold time to TfclkTransmit ATM System Interface Timing Diagram Rfclk Frequency MHz Rfclk Duty CycleRenb Set-up time to Rfclk Renb Hold time to RfclkReceive ATM System Interface Timing Diagram Tfpi Set-up Time to Tclk High Tfpi Hold Time to Tclk HighTclk High to Tfpo Valid RCLK1-4 High to RFPO1-4 Valid239 Jtag Port Interface Timing 241 Ordering and Thermal Information Ordering InformationThermal Information Theta Ja Theta Jc243 Mechanical Information Mechanical Drawing 304 Pin Super Ball Grid Array Sbga245 Contacting PMC-SIERRA, INC Corporate InformationApplication Information Web Site