Manuals / PMC-Sierra / Computer Equipment / Network Router

PMC-Sierra PM5349 manual Register 0xF7 Rase Receive Z1/S1 Bit Type Function Default

Models: PM5349

1 252

Download 252 pages 6.23 Kb

Page 198

		PMC-Sierra, Inc.	PM5349 S/UNI-QUAD
S/UNI-QUAD			PM5349 S/UNI-QUAD
S/UNI-QUAD
DATASHEET


PMC-971239	ISSUE 6		SATURN USER NETWORK INTERFACE (155-QUAD)

Register 0xF7: RASE Receive Z1/S1

Bit	Type	Function	Default
Bit 7	R	Z1/S1[7]	X
Bit 6	R	Z1/S1[6]	X
Bit 5	R	Z1/S1[5]	X
Bit 4	R	Z1/S1[4]	X
Bit 3	R	Z1/S1[3]	X
Bit 2	R	Z1/S1[2]	X
Bit 1	R	Z1/S1[1]	X
Bit 0	R	Z1/S1[0]	X

Z1/S1[3:0]:

The lower nibble of the first Z1/S1 byte contained in the receive stream is extracted into this register. The Z1/S1 byte is used to carry synchronization status messages between line terminating network elements. Z1/S1[3] is the most significant bit corresponding to bit 5, the first bit received. Z1/S1[0] is the least significant bit, corresponding to bit 8, the last bit received. An interrupt may be generated when a byte value is received that differs from the value extracted in the previous frame (using the Z1/S1E bit in the RASE Interrupt Enable Register). In addition, debouncing can be performed where the register is not loaded until eight of the same consecutive nibbles are received. Debouncing is controlled using the Z1/S1_CAP bit in the RASE Configuration/Control register.

Z1/S1[7:4]:

The upper nibble of the first Z1/S1 byte contained in the receive stream is extracted into this register. No interrupt is asserted on the change of this nibble. In addition, when the Z1/S1_CAP bit in the RASE Configuration/Control register selects debouncing, the upper nibble is only updated when eight of the same consecutive lower nibbles are received.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

192

Image 198

PMC-Sierra PM5349 manual Register 0xF7 Rase Receive Z1/S1 Bit Type Function Default

Contents

UNI-QUAD Saturn User Network Interface Issue Issue Date Details of Change Revision HistoryContents Receive Line Overhead Processor Rlop Transmit ATM Cell Processor Txcp Analog Power Supply Filtering Features GeneralSonet Receiver Receive ATM Processor Sonet TransmitterTransmit ATM Processor Applications References Definitions Typical STS-3c STM-1 ATM Switch Port Application Application ExamplesBlock Diagram CS BDescription PM5349 S/UNI-QUAD PIN Diagram Bottom ViewLine Side Interface Signals Pin Name Type Function PIN DescriptionPin Name Type Function Tfpi TclkTDAT8 TfpoTDAT9 TDAT7Tprty TsocTADR3 TenbTADR4 TADR2TCA TfclkDTCA2 DTCA4DTCA3 DTCA1Rprty RsocRenb RADR2 RADR4RADR3 RADR1DRCA2 DRCA4DRCA3 DRCA1RDB Microprocessor Interface Signals Pin Name Type FunctionCSB WRBRstb ALEIntb Jtag Test Access Port TAP Signals Pin Name Type Function Analog Signals Pin Name Type Function Power and Ground Pin Name Type FunctionAB2 VDDAA3 AC1AB1 AB3 VSSAA2 AC2 AC6 AC8QAVD2 QavdAA6 QAVD1 QavsTAVS1A CSU AVSAC3 TAVS1B CSU5V tolerant I/O’s TRSTB, TCK, TMS, TDI, TDOClock Recovery Functional DescriptionReceive Line Interface Crsi Serial to Parallel Converter Receive Section Overhead Processor RsopFramer Error Monitor Loss of SignalDescramble Receive Line Overhead Processor Rlop Error Monitor BlockLoss of Frame Line RDI DetectPM5349 S/UNI-QUAD Bit Error Rate Monitor Synchronization Status ExtractionReceive Path Overhead Processor Rpop Pointer InterpreterLOP AIS Pointer Interpreter Event Indications DescriptionPM5349 S/UNI-QUAD Pointer Interpreter Transition Description SPE Timing Receive ATM Cell Processor Rxcp Cell DelineationDescrambler Cell Filter and HCS VerificationHCS Verification State Diagram Performance Monitor Transmit Line Interface CspiClock Synthesis Line AIS Insert Parallel to Serial ConverterTransmit Section Overhead Processor Tsop BIP-8 InsertTransmit Line Overhead Processor Tlop Framing and Identity InsertScrambler APS InsertLine Febe Insert Transmit Path Overhead Processor TpopPointer Generator Transmit ATM Cell Processor Txcp BIP-8 CalculateFebe Calculate Idle/Unassigned Cell GeneratorReceive ATM Interface HCS GeneratorUtopia Level 2 System Interface Transmit ATM InterfaceJtag Test Access Port Microprocessor InterfaceRegister Memory Map REG Address A100 Description 362 Rxcp FIFO/UTOPIA Control & Config Tpop Path Signal LabelRxcp Configuration 363 Rxcp Interrupt Enables and Counter StatusTxcp Interrupt Enable/Status Txcp ConfigurationTxcp Transmit Cell Status/Configuration Options Rxcp Idle Cell Count LSB 06F 16F 26F 36FRase APS K2 0EF 1EF 2EF 3EFRase APS K1 0FB 1FB 2FB 3FB0FE 1FE 2FE 3FE UNI-QUAD Master Test RegisterReserved for Test Normal Mode Register Description TYPE2 ResetTYPE3 TYPE1TFPOCH0 Bit ReservedTFPOCH1 Tfpo Channel SelectionPM5349 S/UNI-QUAD PHYADR0 PHYADR2PHYADR1 PhyenTfclka TclkaRfclka RefclkaRCLK3A RCLK1ARCLK2A RCLK4ACHNL3I CsuiCHNL4I CHNL2ICsui Chreset TIPAutolrdi AutopfebeAutolfebe AutoprdiLoopt TfpienRxdinv SdleRxdinv PM5349 S/UNI-QUAD Txcpi RaseiCrui RxcpiTxcpi Trooli TroolvTroole PM5349 S/UNI-QUAD Rroolv RrooliRdooli RdoolvRdooli PM5349 S/UNI-QUAD ALGO2 BipwordFoof BipeeDDS Lofi BipeiLosi OofiBipei Bit Type Function Default Bit SBE7 SBE6 SBE5 SBE4 SBE3 SBE2 SBE1 SBE0Register 0x13 Rsop Section BIP-8 MSB Register 0x14 Tsop Control Bit Type Function Default LaisDBIP8 Register 0x15 Tsop Diagnostic Bit Type Function DefaultDlos DFPRegister 0x18 Rlop Control/Status Bit Type Function Default Lrdidet Febei LaiseLrdie LaisiFebee Bit LBE7 LBE6 LBE5 LBE4 LBE3 LBE2 LBE1 LBE0 Register 0x1B Rlop Line BIP-24Bit LBE15 LBE14 LBE13 LBE12 LBE11 LBE10 LBE9 LBE8 Register 0x1C Rlop Line BIP-24 MSB Bit Type Function Default Register 0x1E Rlop Line Febe Register 0x1D Rlop Line Febe LSB Bit Type Function DefaultBit LFE7 LFE6 LFE5 LFE4 LFE3 LFE2 LFE1 LFE0 Bit LFE15 LFE14 LFE13 LFE12 LFE11 LFE10 LFE9 LFE8Register 0x1F Rlop Line Febe MSB Bit Type Function Default Register 0x20 Tlop Control Bit Type Function Default ApsregLrdi Register 0x21 Tlop Diagnostic Bit Type Function Default DbipRegister 0x22 Tlop Transmit K1 Bit Type Function Default Register 0x23 Tlop Transmit K2 Bit Type Function Default PM5349 S/UNI-QUAD Paisonv LopconvLopv PaisvPaisconv PlopvERDIV1 IinvcntERDIV2 ERDIV0Paisi PsliLopi Prdii104 Erdii Invndfi IlljreqiDiscopai Illptri107 Lope PaisePrdie Psle Erdie Invndfe IlljreqeDiscopae Illptre112 Register 0x35 Rpop Pointer LSB Bit Type Function Default Ndfpor ExtdRDI10 115 116 Register 0x38 Rpop Path BIP-8 LSB Bit Type Function Default Bit PBE7 PBE6 PBE5 PBE4 PBE3 PBE2 PBE1 PBE0Register 0x39 Rpop Path BIP-8 MSB Register 0x3A Rpop Path Febe LSB Bit Type Function Default Register 0x3B Rpop Path Febe MSB Bit Type Function DefaultBit PFE7 PFE6 PFE5 PFE4 PFE3 PFE2 PFE1 PFE0 Aprdiv Aprdie Register 0x3C Rpop Auxiliary RDI Bit Type Function DefaultAprdie AprdivBlkbip SOSEnss Blkbipo121 Eprdien EprdisrcPersist 123 PSE FtptrNSE NDF125 CPTR5 CPTR7CPTR6 CPTR4CPTR9 CPTR8APTR5 APTR7APTR6 APTR4Bit NDF3 NDF2 NDF1 NDF0 APTR9APTR8 130 Register 0x49 Tpop Path Status Bit Type Function Default 132 Hcsadd Register 0x60 Rxcp Configuration Bit Type Function DefaultDiscor DdscrHCSFTR1 Register 0x61 Rxcp Configuration Bit Type Function DefaultCcdis HCSFTR0Hcspass Fiforst RxptypRcainv Fiforst RCALEVEL0137 Xfere XferiOVR Fovre139 Uhcsi OocdiChcsi FovriOocdv LCDC7 LCDC9LCDC8 LCDC6Bit GFC3 GFC2 GFC1 GFC0 PTI3 PTI2 PTI1 CLPMGFC1 MGFC3MGFC2 MGFC0CHCS5 CHCS7CHCS6 CHCS4UHCS5 UHCS7UHCS6 UHCS4RCELL5 RCELL7RCELL6 RCELL4148 ICELL5 ICELL7ICELL6 ICELL4ICELL18 ICELL17ICELL16 Dscr Register 0x80 Txcp Configuration Bit Type Function DefaultTptyp HcsbTCALEVEL0 Register 0x81 Txcp Configuration Bit Type Function Default FIFODP1 FIFODP0 Fifo Depth CellsCell H4INSB 156 Tprtyi TprtyeTsoce Tsoci158 Bit GFC3 GFC2 GFC1 GFC0 PTI2 PTI1 PTI0 PAYLD5 PAYLD7PAYLD6 PAYLD4Register 0x87 Txcp Transmit Cell Count 162 Loflrdi SdlrdiSflrdi Loslrdi164 Paisprdi LcdprdiAlrmprdi Lopprdi166 Nopaiseprdi LcdeprdiNoalmeprdi Pslmeprdi168 Paisconprdi NopaisconeprdiLofins SdinsSfins Losins171 Loppais PaisconpaisLopconpais PaispaisPaisen PerdienPrdien LopenAlarm Description Sfbere Bit Z1/S1ESdbere CoapseSfberi PsbfiCoapsi Sdberi177 Sdberten SfbertenSfsmode SdcmodeSfcmode SFSAP5 SFSAP7SFSAP6 SFSAP4SFSAP21 SFSAP23SFSAP22 SFSAP20SFSTH5 SFSTH7SFSTH6 SFSTH4SFDTH5 SFDTH7SFDTH6 SFDTH4SFCTH5 SFCTH7SFCTH6 SFCTH4SDSAP5 SDSAP7SDSAP6 SDSAP4SDSAP21 SDSAP23SDSAP22 SDSAP20SDSTH5 SDSTH7SDSTH6 SDSTH4SDDTH5 SDDTH7SDDTH6 SDDTH4SDCTH5 SDCTH7SDCTH6 SDCTH4Register 0xF5 Rase Receive K1 Bit Type Function Default Register 0xF6 Rase Receive K2 Bit Type Function Default Register 0xF7 Rase Receive Z1/S1 Bit Type Function Default Test Features Description Test Mode Register Memory Map AddressMaster Test Register Register 0x400 Master Test Bit Type Function Default Test Mode 0 Details Test Mode 0 Read LocationsPmcatst Extest Test Mode 0 Write LocationsJtag Test Port Boundary Scan 000Instructions Selected Register Instruction Codes IR20 Identification RegisterBoundary Scan Register Boundary Scan Cells Input PadMUX Output Cell Outcell Bidirectional Cell IocellOutput Enable IocellPAD Operation ATM Mapping into the STS-3c STM-1 SPETransport and Path Overhead Bytes Transport Overhead BytesPath Overhead Bytes PAYLOAD3 PAYLOAD4 ATM Cell Data StructurePAYLOAD1 PAYLOAD2 PAYLOAD5 PAYLOAD6205 Recommended Berm settings Clocking OptionsConceptual Clocking Structure Loopback Operation Line Loopback Mode Serial Diagnostic Loopback Mode Parallel Diagnostic Loopback Mode TDO TMS Control Select Tri-state EnableJtag Support Trstb TCKTAP Controller TAP Controller Finite State Machine Run-Test-Idle States Test-Logic-ResetUpdate-DR Capture-DRBoundary Scan Instructions Update-IRShift-IR BypassIdcode StctestBoard Design Recommendations Power Supply Sequencing Power Sequencing Circuit Analog Power Supply FilteringLAN Mode Analog Power Filters with 3.3V Supply Interfacing to ECL or Pecl DevicesInterfacing to ECL or Pecl Using the S/UNI-QUAD with a 5 Volt ODL Initializing the S/UNI-QUADFunctional Timing ATM Utopia Level 2 System InterfaceMulti-PHY Polling and Addressing Receive Cell Interface 225 Absolute Maximum Ratings Absolute Maximum Ratings16 D.C. Characteristics TBDInput Low Current +10 VIL = GND. Notes 2 Input Low Current 100 VIL = GND. Notes 1Input High Current +10 VIH = VDD. Notes 1 Input High Current +10 VIH = VDD. Notes 2Microprocessor Interface Timing Characteristics Address to Latch Set-up TimeALE CSB+RDB Intb TSALW ALE CSB+WRB TSALW tHALW TV L TSAW tVWR tHAW18 A.C. Timing Characteristics Rstb Pulse Width 100Tenb Set-up time to Tfclk Tfclk Frequency MHzTfclk Duty Cycle Tenb Hold time to TfclkTransmit ATM System Interface Timing Diagram Renb Set-up time to Rfclk Rfclk Frequency MHzRfclk Duty Cycle Renb Hold time to RfclkReceive ATM System Interface Timing Diagram Tclk High to Tfpo Valid Tfpi Set-up Time to Tclk HighTfpi Hold Time to Tclk High RCLK1-4 High to RFPO1-4 Valid239 Jtag Port Interface Timing 241 Thermal Information Ordering and Thermal InformationOrdering Information Theta Ja Theta Jc243 Mechanical Information Mechanical Drawing 304 Pin Super Ball Grid Array Sbga245 Application Information Contacting PMC-SIERRA, INCCorporate Information Web Site