PMC-Sierra PM5349 manual Functional Description, Receive Line Interface Crsi, Clock Recovery

PMC-Sierra, Inc.

S/UNI-QUAD

DATASHEET

PM5349 S/UNI-QUAD

PMC-971239 ISSUE 6 SATURN USER NETWORK INTERFACE (155-QUAD)

10FUNCTIONAL DESCRIPTION

10.1 Receive Line Interface (CRSI)

The Receive Line Interface allows to directly interface the S/UNI-QUAD with optical modules (ODLs) or other medium interfaces. This block performs clock and data recovery and performs serial to parallel conversion on the incoming

155.52 Mbit/s data stream.

10.1.1Clock Recovery

The clock recovery unit recovers the clock from the incoming bit serial data stream. The clock recovery unit is fully compliant with SONET and SDH jitter tolerance requirements. The clock recovery unit utilizes a low frequency reference clock to train and monitor its clock recovery PLL. Under loss of signal conditions, the clock recovery unit continues to output a line rate clock that is locked to this reference for keep alive purposes. The clock recovery unit utilizes a reference clocks at 19.44 MHz. The clock recovery unit provides status bits that indicate whether it is locked to data or the reference. The clock recovery unit also supports diagnostic loopback and a loss of signal input that squelches normal input data.

Initially, the PLL locks to the reference clock, REFCLK. When the frequency of the recovered clock is within 488 ppm of the reference clock, the PLL attempts to lock to the data. Once in data lock, the PLL reverts to the reference clock if no data transitions occur in 80 bit periods or if the recovered clock drifts beyond 488 ppm of the reference clock.

When the transmit clock is derived from the recovered clock (loop timing), the accuracy of the transmit clock is directly related to the REFCLK reference accuracy in the case of a loss of signal condition. To meet the Bellcore GR-253- CORE SONET Network Element free-run accuracy specification, the reference must be within +/-20ppm. When not loop timed, the REFCLK accuracy may be relaxed to +/-50ppm.

The loop filter transfer function is optimized to enable the PLL to track the jitter, yet tolerate the minimum transition density expected in a received SONET/SDH data signal. The total loop dynamics of the clock recovery PLL yield a jitter tolerance that exceeds the minimum tolerance proposed for SONET equipment by GR-253-CORE (Figure 3).

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 32